Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45142595	1			T1	921		T2	6138		T3	1541
triple_byte_access	2554566	1			T1	18		T3	1381		T4	1970
halfword_access	3835966	1			T1	23		T3	2061		T4	3021
byte_access	5123949	1			T1	50		T3	2874		T4	4041
zero_access	1288506	1			T1	14		T3	660		T4	981

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28917153

1

T1

494

T2

3088

T3

4254

auto[1]

29028429

1

T1

532

T2

3050

T3

4263

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22519846	1			T1	445		T2	3088		T3	803
auto[0]	triple_byte_access	1273538	1			T1	11		T3	671		T4	1000
auto[0]	halfword_access	1914217	1			T1	11		T3	1035		T4	1522
auto[0]	byte_access	2560717	1			T1	21		T3	1413		T4	2051
auto[0]	zero_access	648835	1			T1	6		T3	332		T4	471
auto[1]	word_access	22622749	1			T1	476		T2	3050		T3	738
auto[1]	triple_byte_access	1281028	1			T1	7		T3	710		T4	970
auto[1]	halfword_access	1921749	1			T1	12		T3	1026		T4	1499
auto[1]	byte_access	2563232	1			T1	29		T3	1461		T4	1990
auto[1]	zero_access	639671	1			T1	8		T3	328		T4	510