| T31 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3639846972 |
|
|
Aug 14 05:04:31 PM PDT 24 |
Aug 14 05:04:35 PM PDT 24 |
918464151 ps |
| T799 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3424190551 |
|
|
Aug 14 05:04:52 PM PDT 24 |
Aug 14 05:07:06 PM PDT 24 |
7126801514 ps |
| T800 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3552276462 |
|
|
Aug 14 05:07:49 PM PDT 24 |
Aug 14 05:26:32 PM PDT 24 |
68921397913 ps |
| T801 |
/workspace/coverage/default/5.sram_ctrl_alert_test.291867009 |
|
|
Aug 14 05:04:49 PM PDT 24 |
Aug 14 05:04:50 PM PDT 24 |
15558523 ps |
| T802 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1201940414 |
|
|
Aug 14 05:07:18 PM PDT 24 |
Aug 14 05:08:59 PM PDT 24 |
568084115 ps |
| T803 |
/workspace/coverage/default/14.sram_ctrl_alert_test.876596135 |
|
|
Aug 14 05:05:27 PM PDT 24 |
Aug 14 05:05:28 PM PDT 24 |
12948933 ps |
| T804 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2499903520 |
|
|
Aug 14 05:05:24 PM PDT 24 |
Aug 14 05:18:26 PM PDT 24 |
33204164201 ps |
| T805 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3591063900 |
|
|
Aug 14 05:06:19 PM PDT 24 |
Aug 14 05:06:29 PM PDT 24 |
246873244 ps |
| T806 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3989862315 |
|
|
Aug 14 05:08:07 PM PDT 24 |
Aug 14 05:14:59 PM PDT 24 |
17979991178 ps |
| T807 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3235761335 |
|
|
Aug 14 05:06:25 PM PDT 24 |
Aug 14 05:06:30 PM PDT 24 |
147394159 ps |
| T808 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1523980407 |
|
|
Aug 14 05:07:47 PM PDT 24 |
Aug 14 05:07:48 PM PDT 24 |
29180885 ps |
| T809 |
/workspace/coverage/default/17.sram_ctrl_executable.3379861193 |
|
|
Aug 14 05:05:50 PM PDT 24 |
Aug 14 05:16:03 PM PDT 24 |
14824801495 ps |
| T810 |
/workspace/coverage/default/39.sram_ctrl_regwen.2646494175 |
|
|
Aug 14 05:07:57 PM PDT 24 |
Aug 14 05:19:21 PM PDT 24 |
8625732274 ps |
| T811 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4241149525 |
|
|
Aug 14 05:06:44 PM PDT 24 |
Aug 14 05:06:50 PM PDT 24 |
299906170 ps |
| T812 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1168823715 |
|
|
Aug 14 05:06:19 PM PDT 24 |
Aug 14 05:06:25 PM PDT 24 |
624099697 ps |
| T813 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.364926197 |
|
|
Aug 14 05:05:02 PM PDT 24 |
Aug 14 05:05:06 PM PDT 24 |
53496605 ps |
| T814 |
/workspace/coverage/default/49.sram_ctrl_executable.4164139156 |
|
|
Aug 14 05:09:07 PM PDT 24 |
Aug 14 05:32:18 PM PDT 24 |
73190354205 ps |
| T815 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2631165188 |
|
|
Aug 14 05:08:45 PM PDT 24 |
Aug 14 05:52:30 PM PDT 24 |
10603515038 ps |
| T816 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3398716920 |
|
|
Aug 14 05:05:22 PM PDT 24 |
Aug 14 05:05:32 PM PDT 24 |
2907153016 ps |
| T817 |
/workspace/coverage/default/4.sram_ctrl_regwen.3345827892 |
|
|
Aug 14 05:04:49 PM PDT 24 |
Aug 14 05:30:23 PM PDT 24 |
16137333344 ps |
| T818 |
/workspace/coverage/default/10.sram_ctrl_stress_all.3641890608 |
|
|
Aug 14 05:05:24 PM PDT 24 |
Aug 14 05:57:04 PM PDT 24 |
39456489323 ps |
| T819 |
/workspace/coverage/default/17.sram_ctrl_alert_test.626148287 |
|
|
Aug 14 05:05:52 PM PDT 24 |
Aug 14 05:05:53 PM PDT 24 |
20739559 ps |
| T820 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.816989473 |
|
|
Aug 14 05:08:25 PM PDT 24 |
Aug 14 05:13:27 PM PDT 24 |
12744403278 ps |
| T821 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1069247233 |
|
|
Aug 14 05:08:16 PM PDT 24 |
Aug 14 05:08:28 PM PDT 24 |
198607867 ps |
| T822 |
/workspace/coverage/default/2.sram_ctrl_regwen.349019574 |
|
|
Aug 14 05:04:30 PM PDT 24 |
Aug 14 05:13:33 PM PDT 24 |
3318511173 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_regwen.3349813906 |
|
|
Aug 14 05:07:47 PM PDT 24 |
Aug 14 05:09:49 PM PDT 24 |
1152931222 ps |
| T824 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.4074649053 |
|
|
Aug 14 05:09:06 PM PDT 24 |
Aug 14 05:09:12 PM PDT 24 |
226774913 ps |
| T825 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.448393297 |
|
|
Aug 14 05:08:48 PM PDT 24 |
Aug 14 05:08:54 PM PDT 24 |
456210610 ps |
| T826 |
/workspace/coverage/default/9.sram_ctrl_executable.2590472370 |
|
|
Aug 14 05:05:10 PM PDT 24 |
Aug 14 05:21:40 PM PDT 24 |
3220334277 ps |
| T827 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.381300652 |
|
|
Aug 14 05:06:02 PM PDT 24 |
Aug 14 05:06:06 PM PDT 24 |
97213526 ps |
| T828 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1359270688 |
|
|
Aug 14 05:04:42 PM PDT 24 |
Aug 14 05:04:48 PM PDT 24 |
764158201 ps |
| T829 |
/workspace/coverage/default/4.sram_ctrl_alert_test.1850581824 |
|
|
Aug 14 05:04:52 PM PDT 24 |
Aug 14 05:04:52 PM PDT 24 |
22036736 ps |
| T830 |
/workspace/coverage/default/7.sram_ctrl_executable.1889133579 |
|
|
Aug 14 05:05:00 PM PDT 24 |
Aug 14 05:18:21 PM PDT 24 |
18703956874 ps |
| T831 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.180584888 |
|
|
Aug 14 05:06:53 PM PDT 24 |
Aug 14 05:32:22 PM PDT 24 |
13653826987 ps |
| T832 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1417901292 |
|
|
Aug 14 05:05:21 PM PDT 24 |
Aug 14 05:05:24 PM PDT 24 |
88273817 ps |
| T833 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2286452574 |
|
|
Aug 14 05:05:30 PM PDT 24 |
Aug 14 05:10:05 PM PDT 24 |
10476766383 ps |
| T834 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2163642164 |
|
|
Aug 14 05:07:47 PM PDT 24 |
Aug 14 05:09:31 PM PDT 24 |
330367481 ps |
| T835 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.4135924128 |
|
|
Aug 14 05:05:50 PM PDT 24 |
Aug 14 05:07:28 PM PDT 24 |
2279800087 ps |
| T836 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1113628171 |
|
|
Aug 14 05:06:25 PM PDT 24 |
Aug 14 05:12:10 PM PDT 24 |
18620526284 ps |
| T837 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2110381324 |
|
|
Aug 14 05:06:53 PM PDT 24 |
Aug 14 05:06:53 PM PDT 24 |
32264652 ps |
| T838 |
/workspace/coverage/default/4.sram_ctrl_smoke.1235492792 |
|
|
Aug 14 05:04:40 PM PDT 24 |
Aug 14 05:04:47 PM PDT 24 |
234848181 ps |
| T839 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.480168862 |
|
|
Aug 14 05:04:30 PM PDT 24 |
Aug 14 05:04:34 PM PDT 24 |
739856781 ps |
| T47 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3687065384 |
|
|
Aug 14 05:06:07 PM PDT 24 |
Aug 14 05:08:23 PM PDT 24 |
1418506139 ps |
| T840 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3907642852 |
|
|
Aug 14 05:05:10 PM PDT 24 |
Aug 14 05:05:23 PM PDT 24 |
607292321 ps |
| T841 |
/workspace/coverage/default/35.sram_ctrl_executable.4044293102 |
|
|
Aug 14 05:07:33 PM PDT 24 |
Aug 14 05:25:52 PM PDT 24 |
36135351577 ps |
| T129 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2539621972 |
|
|
Aug 14 05:06:44 PM PDT 24 |
Aug 14 05:07:04 PM PDT 24 |
2349106713 ps |
| T842 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2889270314 |
|
|
Aug 14 05:05:12 PM PDT 24 |
Aug 14 05:12:41 PM PDT 24 |
4536824594 ps |
| T843 |
/workspace/coverage/default/27.sram_ctrl_smoke.4065800074 |
|
|
Aug 14 05:06:33 PM PDT 24 |
Aug 14 05:06:46 PM PDT 24 |
428408442 ps |
| T844 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2270092437 |
|
|
Aug 14 05:04:51 PM PDT 24 |
Aug 14 05:05:14 PM PDT 24 |
2890687228 ps |
| T845 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4222872865 |
|
|
Aug 14 05:05:21 PM PDT 24 |
Aug 14 05:19:02 PM PDT 24 |
11202373347 ps |
| T846 |
/workspace/coverage/default/3.sram_ctrl_stress_all.4270697617 |
|
|
Aug 14 05:04:39 PM PDT 24 |
Aug 14 06:03:17 PM PDT 24 |
53742147883 ps |
| T847 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2473681628 |
|
|
Aug 14 05:08:58 PM PDT 24 |
Aug 14 05:08:59 PM PDT 24 |
41189874 ps |
| T848 |
/workspace/coverage/default/33.sram_ctrl_smoke.247555643 |
|
|
Aug 14 05:07:19 PM PDT 24 |
Aug 14 05:07:55 PM PDT 24 |
86954574 ps |
| T130 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.872693272 |
|
|
Aug 14 05:07:21 PM PDT 24 |
Aug 14 05:09:31 PM PDT 24 |
3234681279 ps |
| T849 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1131210183 |
|
|
Aug 14 05:07:47 PM PDT 24 |
Aug 14 05:15:28 PM PDT 24 |
4738292655 ps |
| T850 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2516448913 |
|
|
Aug 14 05:09:00 PM PDT 24 |
Aug 14 05:09:06 PM PDT 24 |
1674145506 ps |
| T851 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4117854495 |
|
|
Aug 14 05:05:31 PM PDT 24 |
Aug 14 05:05:55 PM PDT 24 |
89043498 ps |
| T852 |
/workspace/coverage/default/35.sram_ctrl_bijection.2251072904 |
|
|
Aug 14 05:07:21 PM PDT 24 |
Aug 14 05:07:53 PM PDT 24 |
500948354 ps |
| T853 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.163323046 |
|
|
Aug 14 05:08:15 PM PDT 24 |
Aug 14 05:13:46 PM PDT 24 |
13162812832 ps |
| T854 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.407479483 |
|
|
Aug 14 05:05:49 PM PDT 24 |
Aug 14 05:05:55 PM PDT 24 |
240136337 ps |
| T855 |
/workspace/coverage/default/41.sram_ctrl_executable.695510535 |
|
|
Aug 14 05:08:06 PM PDT 24 |
Aug 14 05:22:43 PM PDT 24 |
2003710675 ps |
| T856 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3984431703 |
|
|
Aug 14 05:04:50 PM PDT 24 |
Aug 14 05:04:58 PM PDT 24 |
1188649283 ps |
| T857 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.531403929 |
|
|
Aug 14 05:07:21 PM PDT 24 |
Aug 14 05:07:33 PM PDT 24 |
680026851 ps |
| T858 |
/workspace/coverage/default/22.sram_ctrl_bijection.2652930759 |
|
|
Aug 14 05:06:08 PM PDT 24 |
Aug 14 05:07:18 PM PDT 24 |
17113593692 ps |
| T859 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2793400065 |
|
|
Aug 14 05:09:07 PM PDT 24 |
Aug 14 05:09:08 PM PDT 24 |
67863854 ps |
| T860 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2870100243 |
|
|
Aug 14 05:08:49 PM PDT 24 |
Aug 14 05:08:59 PM PDT 24 |
407107607 ps |
| T861 |
/workspace/coverage/default/44.sram_ctrl_smoke.1810336783 |
|
|
Aug 14 05:08:23 PM PDT 24 |
Aug 14 05:08:33 PM PDT 24 |
660092810 ps |
| T862 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2578987 |
|
|
Aug 14 05:05:21 PM PDT 24 |
Aug 14 05:08:18 PM PDT 24 |
3138494640 ps |
| T863 |
/workspace/coverage/default/41.sram_ctrl_regwen.1416464962 |
|
|
Aug 14 05:08:04 PM PDT 24 |
Aug 14 05:26:38 PM PDT 24 |
21612723984 ps |
| T864 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.739071033 |
|
|
Aug 14 05:07:20 PM PDT 24 |
Aug 14 05:08:55 PM PDT 24 |
1444487382 ps |
| T865 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.487048879 |
|
|
Aug 14 05:05:10 PM PDT 24 |
Aug 14 05:05:15 PM PDT 24 |
65724064 ps |
| T866 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.3914394684 |
|
|
Aug 14 05:05:58 PM PDT 24 |
Aug 14 05:06:06 PM PDT 24 |
157748334 ps |
| T867 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.4134989777 |
|
|
Aug 14 05:06:08 PM PDT 24 |
Aug 14 05:12:36 PM PDT 24 |
63359329886 ps |
| T868 |
/workspace/coverage/default/43.sram_ctrl_executable.3746525652 |
|
|
Aug 14 05:08:22 PM PDT 24 |
Aug 14 05:28:17 PM PDT 24 |
12789048479 ps |
| T869 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2854173739 |
|
|
Aug 14 05:04:41 PM PDT 24 |
Aug 14 05:04:44 PM PDT 24 |
376279205 ps |
| T870 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3481737526 |
|
|
Aug 14 05:06:20 PM PDT 24 |
Aug 14 05:06:32 PM PDT 24 |
354805166 ps |
| T871 |
/workspace/coverage/default/45.sram_ctrl_executable.1823294031 |
|
|
Aug 14 05:08:33 PM PDT 24 |
Aug 14 05:22:24 PM PDT 24 |
15794639484 ps |
| T872 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1046373391 |
|
|
Aug 14 05:08:17 PM PDT 24 |
Aug 14 05:08:36 PM PDT 24 |
87438702 ps |
| T873 |
/workspace/coverage/default/27.sram_ctrl_partial_access.3020367639 |
|
|
Aug 14 05:06:35 PM PDT 24 |
Aug 14 05:06:42 PM PDT 24 |
512108593 ps |
| T874 |
/workspace/coverage/default/35.sram_ctrl_regwen.1210437684 |
|
|
Aug 14 05:07:31 PM PDT 24 |
Aug 14 05:32:07 PM PDT 24 |
22120246716 ps |
| T875 |
/workspace/coverage/default/33.sram_ctrl_regwen.1903185813 |
|
|
Aug 14 05:07:19 PM PDT 24 |
Aug 14 05:11:26 PM PDT 24 |
2487337995 ps |
| T876 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3730596265 |
|
|
Aug 14 05:05:31 PM PDT 24 |
Aug 14 05:05:37 PM PDT 24 |
6652451339 ps |
| T877 |
/workspace/coverage/default/30.sram_ctrl_executable.1503015366 |
|
|
Aug 14 05:07:01 PM PDT 24 |
Aug 14 05:15:34 PM PDT 24 |
1152623133 ps |
| T878 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1628449421 |
|
|
Aug 14 05:05:30 PM PDT 24 |
Aug 14 05:14:24 PM PDT 24 |
6257499869 ps |
| T879 |
/workspace/coverage/default/3.sram_ctrl_smoke.2062178415 |
|
|
Aug 14 05:04:40 PM PDT 24 |
Aug 14 05:04:48 PM PDT 24 |
154293892 ps |
| T880 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.1543381394 |
|
|
Aug 14 05:06:24 PM PDT 24 |
Aug 14 05:06:56 PM PDT 24 |
182688314 ps |
| T881 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1911885921 |
|
|
Aug 14 05:06:02 PM PDT 24 |
Aug 14 05:23:39 PM PDT 24 |
10738694532 ps |
| T882 |
/workspace/coverage/default/18.sram_ctrl_executable.3317703642 |
|
|
Aug 14 05:05:49 PM PDT 24 |
Aug 14 05:28:12 PM PDT 24 |
17377328727 ps |
| T883 |
/workspace/coverage/default/37.sram_ctrl_smoke.263591436 |
|
|
Aug 14 05:07:48 PM PDT 24 |
Aug 14 05:08:42 PM PDT 24 |
495061025 ps |
| T884 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.736474653 |
|
|
Aug 14 05:06:34 PM PDT 24 |
Aug 14 05:06:45 PM PDT 24 |
2612257055 ps |
| T885 |
/workspace/coverage/default/25.sram_ctrl_stress_all.921071550 |
|
|
Aug 14 05:06:26 PM PDT 24 |
Aug 14 05:52:33 PM PDT 24 |
21472227697 ps |
| T886 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1615038759 |
|
|
Aug 14 05:05:31 PM PDT 24 |
Aug 14 05:05:35 PM PDT 24 |
573502188 ps |
| T887 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2102123816 |
|
|
Aug 14 05:08:08 PM PDT 24 |
Aug 14 05:13:50 PM PDT 24 |
18115689062 ps |
| T888 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2979101180 |
|
|
Aug 14 05:05:01 PM PDT 24 |
Aug 14 05:05:02 PM PDT 24 |
32248044 ps |
| T889 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3994939653 |
|
|
Aug 14 05:08:08 PM PDT 24 |
Aug 14 05:16:24 PM PDT 24 |
6734749417 ps |
| T890 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1242865298 |
|
|
Aug 14 05:08:43 PM PDT 24 |
Aug 14 05:08:51 PM PDT 24 |
2076341980 ps |
| T891 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1873517854 |
|
|
Aug 14 05:06:24 PM PDT 24 |
Aug 14 05:10:53 PM PDT 24 |
2795387402 ps |
| T892 |
/workspace/coverage/default/15.sram_ctrl_regwen.3512204752 |
|
|
Aug 14 05:05:38 PM PDT 24 |
Aug 14 05:12:42 PM PDT 24 |
35533959349 ps |
| T893 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.6387518 |
|
|
Aug 14 05:05:09 PM PDT 24 |
Aug 14 05:05:13 PM PDT 24 |
632831237 ps |
| T894 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1289237647 |
|
|
Aug 14 05:07:37 PM PDT 24 |
Aug 14 05:07:49 PM PDT 24 |
3422886566 ps |
| T895 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1050655626 |
|
|
Aug 14 05:04:52 PM PDT 24 |
Aug 14 05:05:19 PM PDT 24 |
99457515 ps |
| T896 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2492031707 |
|
|
Aug 14 05:06:42 PM PDT 24 |
Aug 14 05:06:43 PM PDT 24 |
27960793 ps |
| T897 |
/workspace/coverage/default/29.sram_ctrl_smoke.3844423314 |
|
|
Aug 14 05:06:42 PM PDT 24 |
Aug 14 05:08:02 PM PDT 24 |
2131433194 ps |
| T898 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1967387631 |
|
|
Aug 14 05:07:24 PM PDT 24 |
Aug 14 05:10:46 PM PDT 24 |
19264139275 ps |
| T899 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2699227305 |
|
|
Aug 14 05:05:58 PM PDT 24 |
Aug 14 05:09:09 PM PDT 24 |
3880392721 ps |
| T900 |
/workspace/coverage/default/6.sram_ctrl_regwen.2877565694 |
|
|
Aug 14 05:05:01 PM PDT 24 |
Aug 14 05:11:56 PM PDT 24 |
1403727434 ps |
| T901 |
/workspace/coverage/default/47.sram_ctrl_regwen.1647388721 |
|
|
Aug 14 05:08:49 PM PDT 24 |
Aug 14 05:09:27 PM PDT 24 |
339815362 ps |
| T902 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3956996262 |
|
|
Aug 14 05:06:13 PM PDT 24 |
Aug 14 05:06:14 PM PDT 24 |
26169569 ps |
| T903 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3015958678 |
|
|
Aug 14 05:08:18 PM PDT 24 |
Aug 14 06:30:28 PM PDT 24 |
257143487649 ps |
| T904 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2171647145 |
|
|
Aug 14 05:08:23 PM PDT 24 |
Aug 14 05:14:51 PM PDT 24 |
32137843567 ps |
| T905 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2668888082 |
|
|
Aug 14 05:07:30 PM PDT 24 |
Aug 14 05:07:33 PM PDT 24 |
194105771 ps |
| T906 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.1190578017 |
|
|
Aug 14 05:09:09 PM PDT 24 |
Aug 14 05:09:25 PM PDT 24 |
261881714 ps |
| T907 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1613965313 |
|
|
Aug 14 05:05:38 PM PDT 24 |
Aug 14 05:24:29 PM PDT 24 |
135936261658 ps |
| T908 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1504354850 |
|
|
Aug 14 05:07:04 PM PDT 24 |
Aug 14 05:08:34 PM PDT 24 |
570771682 ps |
| T909 |
/workspace/coverage/default/43.sram_ctrl_bijection.2401390789 |
|
|
Aug 14 05:08:14 PM PDT 24 |
Aug 14 05:08:44 PM PDT 24 |
1354754182 ps |
| T910 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.993877813 |
|
|
Aug 14 05:06:53 PM PDT 24 |
Aug 14 05:07:41 PM PDT 24 |
101520094 ps |
| T911 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.28058379 |
|
|
Aug 14 05:08:40 PM PDT 24 |
Aug 14 05:09:24 PM PDT 24 |
1344224470 ps |
| T912 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3735303592 |
|
|
Aug 14 05:05:40 PM PDT 24 |
Aug 14 05:07:51 PM PDT 24 |
212246161 ps |
| T913 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2380105792 |
|
|
Aug 14 05:05:50 PM PDT 24 |
Aug 14 05:06:14 PM PDT 24 |
91252501 ps |
| T914 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.654371802 |
|
|
Aug 14 05:04:43 PM PDT 24 |
Aug 14 05:05:01 PM PDT 24 |
91072923 ps |
| T915 |
/workspace/coverage/default/1.sram_ctrl_bijection.758172305 |
|
|
Aug 14 05:04:33 PM PDT 24 |
Aug 14 05:05:07 PM PDT 24 |
3049105808 ps |
| T916 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.421276461 |
|
|
Aug 14 05:05:58 PM PDT 24 |
Aug 14 05:06:04 PM PDT 24 |
478930058 ps |
| T917 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1476639456 |
|
|
Aug 14 05:04:40 PM PDT 24 |
Aug 14 05:05:11 PM PDT 24 |
92126076 ps |
| T918 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2261691430 |
|
|
Aug 14 05:06:26 PM PDT 24 |
Aug 14 05:27:28 PM PDT 24 |
19537781275 ps |
| T919 |
/workspace/coverage/default/38.sram_ctrl_alert_test.1420082874 |
|
|
Aug 14 05:07:47 PM PDT 24 |
Aug 14 05:07:48 PM PDT 24 |
75386277 ps |
| T920 |
/workspace/coverage/default/2.sram_ctrl_smoke.3851672260 |
|
|
Aug 14 05:04:30 PM PDT 24 |
Aug 14 05:04:38 PM PDT 24 |
938672224 ps |
| T921 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1789280022 |
|
|
Aug 14 05:08:25 PM PDT 24 |
Aug 14 05:28:02 PM PDT 24 |
3571690759 ps |
| T922 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3099364811 |
|
|
Aug 14 05:08:58 PM PDT 24 |
Aug 14 06:30:00 PM PDT 24 |
300531490265 ps |
| T923 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1260338737 |
|
|
Aug 14 05:05:20 PM PDT 24 |
Aug 14 05:05:28 PM PDT 24 |
63012995 ps |
| T924 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.206866430 |
|
|
Aug 14 05:09:07 PM PDT 24 |
Aug 14 05:28:19 PM PDT 24 |
4260013817 ps |
| T925 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.737928507 |
|
|
Aug 14 05:04:40 PM PDT 24 |
Aug 14 05:16:04 PM PDT 24 |
8715777552 ps |
| T926 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2729510262 |
|
|
Aug 14 05:08:33 PM PDT 24 |
Aug 14 05:14:26 PM PDT 24 |
14143276385 ps |
| T927 |
/workspace/coverage/default/12.sram_ctrl_regwen.4220188090 |
|
|
Aug 14 05:05:23 PM PDT 24 |
Aug 14 05:07:20 PM PDT 24 |
835206851 ps |
| T928 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.886408325 |
|
|
Aug 14 05:04:29 PM PDT 24 |
Aug 14 05:42:39 PM PDT 24 |
5287355622 ps |
| T929 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3732524166 |
|
|
Aug 14 05:08:15 PM PDT 24 |
Aug 14 05:12:20 PM PDT 24 |
3074176362 ps |
| T930 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2882274929 |
|
|
Aug 14 05:08:17 PM PDT 24 |
Aug 14 05:08:19 PM PDT 24 |
388128643 ps |
| T931 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.4148016966 |
|
|
Aug 14 05:07:19 PM PDT 24 |
Aug 14 05:07:19 PM PDT 24 |
42552334 ps |
| T932 |
/workspace/coverage/default/8.sram_ctrl_bijection.3285559585 |
|
|
Aug 14 05:05:09 PM PDT 24 |
Aug 14 05:06:17 PM PDT 24 |
1056712519 ps |
| T933 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.179402223 |
|
|
Aug 14 05:07:04 PM PDT 24 |
Aug 14 05:07:10 PM PDT 24 |
343847729 ps |
| T934 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1298966702 |
|
|
Aug 14 05:07:24 PM PDT 24 |
Aug 14 05:08:42 PM PDT 24 |
150501808 ps |
| T935 |
/workspace/coverage/default/48.sram_ctrl_bijection.2766586911 |
|
|
Aug 14 05:08:56 PM PDT 24 |
Aug 14 05:10:00 PM PDT 24 |
2180509165 ps |
| T936 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2149326235 |
|
|
Aug 14 05:06:35 PM PDT 24 |
Aug 14 05:10:08 PM PDT 24 |
1451139586 ps |
| T66 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.942368390 |
|
|
Aug 14 04:26:44 PM PDT 24 |
Aug 14 04:26:46 PM PDT 24 |
339324695 ps |
| T67 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1653205846 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
499600313 ps |
| T70 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3208426285 |
|
|
Aug 14 04:26:48 PM PDT 24 |
Aug 14 04:26:49 PM PDT 24 |
65605259 ps |
| T81 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2293860173 |
|
|
Aug 14 04:26:34 PM PDT 24 |
Aug 14 04:26:35 PM PDT 24 |
16557813 ps |
| T68 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3817785452 |
|
|
Aug 14 04:26:47 PM PDT 24 |
Aug 14 04:26:50 PM PDT 24 |
323948945 ps |
| T82 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1390624192 |
|
|
Aug 14 04:26:37 PM PDT 24 |
Aug 14 04:26:38 PM PDT 24 |
21825863 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3342503149 |
|
|
Aug 14 04:26:41 PM PDT 24 |
Aug 14 04:26:43 PM PDT 24 |
850987370 ps |
| T937 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2397577140 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
98626208 ps |
| T134 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.53725769 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
456879764 ps |
| T84 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3862370420 |
|
|
Aug 14 04:26:31 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
20223300 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3622504734 |
|
|
Aug 14 04:26:38 PM PDT 24 |
Aug 14 04:26:39 PM PDT 24 |
13551702 ps |
| T938 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.380698449 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
96777972 ps |
| T939 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4103758177 |
|
|
Aug 14 04:26:32 PM PDT 24 |
Aug 14 04:26:33 PM PDT 24 |
36023724 ps |
| T940 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.548115711 |
|
|
Aug 14 04:26:52 PM PDT 24 |
Aug 14 04:26:56 PM PDT 24 |
132961857 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1194124012 |
|
|
Aug 14 04:27:12 PM PDT 24 |
Aug 14 04:27:16 PM PDT 24 |
557486769 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.665425702 |
|
|
Aug 14 04:26:18 PM PDT 24 |
Aug 14 04:26:19 PM PDT 24 |
33216740 ps |
| T140 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4023864382 |
|
|
Aug 14 04:26:46 PM PDT 24 |
Aug 14 04:26:48 PM PDT 24 |
1335591379 ps |
| T122 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.928084970 |
|
|
Aug 14 04:26:58 PM PDT 24 |
Aug 14 04:26:58 PM PDT 24 |
30810623 ps |
| T123 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2599163737 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:28 PM PDT 24 |
12772360 ps |
| T135 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1244335746 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
701777824 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3591394105 |
|
|
Aug 14 04:26:50 PM PDT 24 |
Aug 14 04:26:53 PM PDT 24 |
68909197 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4086930941 |
|
|
Aug 14 04:26:32 PM PDT 24 |
Aug 14 04:26:33 PM PDT 24 |
20574023 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1930351144 |
|
|
Aug 14 04:26:30 PM PDT 24 |
Aug 14 04:26:31 PM PDT 24 |
14899883 ps |
| T118 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.409201389 |
|
|
Aug 14 04:26:57 PM PDT 24 |
Aug 14 04:27:00 PM PDT 24 |
1652206617 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1795845174 |
|
|
Aug 14 04:26:45 PM PDT 24 |
Aug 14 04:26:45 PM PDT 24 |
72643924 ps |
| T942 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1461281757 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:28 PM PDT 24 |
12559730 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2833267773 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:31 PM PDT 24 |
929758887 ps |
| T943 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.983199240 |
|
|
Aug 14 04:26:14 PM PDT 24 |
Aug 14 04:26:15 PM PDT 24 |
24638311 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3073743441 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:29 PM PDT 24 |
68456928 ps |
| T100 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1066940815 |
|
|
Aug 14 04:26:44 PM PDT 24 |
Aug 14 04:26:44 PM PDT 24 |
50787445 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1182010263 |
|
|
Aug 14 04:26:48 PM PDT 24 |
Aug 14 04:26:49 PM PDT 24 |
125730322 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1427169371 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
12489098 ps |
| T101 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.767360365 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
2266191067 ps |
| T102 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2104018360 |
|
|
Aug 14 04:27:06 PM PDT 24 |
Aug 14 04:27:08 PM PDT 24 |
815316684 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2401243486 |
|
|
Aug 14 04:26:30 PM PDT 24 |
Aug 14 04:26:31 PM PDT 24 |
61277739 ps |
| T119 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3185178577 |
|
|
Aug 14 04:27:04 PM PDT 24 |
Aug 14 04:27:06 PM PDT 24 |
764872117 ps |
| T103 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3931088467 |
|
|
Aug 14 04:26:43 PM PDT 24 |
Aug 14 04:26:47 PM PDT 24 |
805492900 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2384345831 |
|
|
Aug 14 04:26:31 PM PDT 24 |
Aug 14 04:26:34 PM PDT 24 |
115419447 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4215361036 |
|
|
Aug 14 04:26:52 PM PDT 24 |
Aug 14 04:26:53 PM PDT 24 |
37801922 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.299630690 |
|
|
Aug 14 04:26:31 PM PDT 24 |
Aug 14 04:26:33 PM PDT 24 |
22019016 ps |
| T951 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2420825346 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
106432084 ps |
| T952 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1739380682 |
|
|
Aug 14 04:26:36 PM PDT 24 |
Aug 14 04:26:37 PM PDT 24 |
33674655 ps |
| T953 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3724631236 |
|
|
Aug 14 04:26:46 PM PDT 24 |
Aug 14 04:26:47 PM PDT 24 |
47930241 ps |
| T104 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3509029151 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
31549488 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1822328894 |
|
|
Aug 14 04:26:50 PM PDT 24 |
Aug 14 04:26:56 PM PDT 24 |
18311000 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1536860908 |
|
|
Aug 14 04:26:32 PM PDT 24 |
Aug 14 04:26:37 PM PDT 24 |
1062016106 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1952134903 |
|
|
Aug 14 04:26:45 PM PDT 24 |
Aug 14 04:26:46 PM PDT 24 |
86043366 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.621392516 |
|
|
Aug 14 04:26:17 PM PDT 24 |
Aug 14 04:26:19 PM PDT 24 |
95963684 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.239128192 |
|
|
Aug 14 04:26:32 PM PDT 24 |
Aug 14 04:26:33 PM PDT 24 |
43922217 ps |
| T959 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.74269780 |
|
|
Aug 14 04:26:48 PM PDT 24 |
Aug 14 04:27:02 PM PDT 24 |
51869794 ps |
| T109 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.95224068 |
|
|
Aug 14 04:26:48 PM PDT 24 |
Aug 14 04:26:49 PM PDT 24 |
25948995 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3184676314 |
|
|
Aug 14 04:26:20 PM PDT 24 |
Aug 14 04:26:22 PM PDT 24 |
42965229 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3188366425 |
|
|
Aug 14 04:26:52 PM PDT 24 |
Aug 14 04:26:57 PM PDT 24 |
1739218231 ps |
| T116 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.862707820 |
|
|
Aug 14 04:26:56 PM PDT 24 |
Aug 14 04:27:00 PM PDT 24 |
860469386 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.298075300 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:28 PM PDT 24 |
13563401 ps |
| T111 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.928985406 |
|
|
Aug 14 04:26:41 PM PDT 24 |
Aug 14 04:26:43 PM PDT 24 |
175761479 ps |
| T137 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.681969953 |
|
|
Aug 14 04:26:31 PM PDT 24 |
Aug 14 04:26:34 PM PDT 24 |
1808928971 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3908210060 |
|
|
Aug 14 04:26:33 PM PDT 24 |
Aug 14 04:26:34 PM PDT 24 |
14527602 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2912738474 |
|
|
Aug 14 04:26:42 PM PDT 24 |
Aug 14 04:26:43 PM PDT 24 |
127103555 ps |
| T136 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3329264185 |
|
|
Aug 14 04:26:44 PM PDT 24 |
Aug 14 04:26:47 PM PDT 24 |
648888384 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1928980522 |
|
|
Aug 14 04:26:45 PM PDT 24 |
Aug 14 04:26:46 PM PDT 24 |
25496959 ps |
| T138 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3797989713 |
|
|
Aug 14 04:26:45 PM PDT 24 |
Aug 14 04:26:47 PM PDT 24 |
232882810 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4112740442 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:28 PM PDT 24 |
28950422 ps |
| T139 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1335258250 |
|
|
Aug 14 04:26:45 PM PDT 24 |
Aug 14 04:26:48 PM PDT 24 |
347299648 ps |
| T967 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2536886846 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:29 PM PDT 24 |
51092162 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1579217352 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
24680864 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3317557785 |
|
|
Aug 14 04:26:49 PM PDT 24 |
Aug 14 04:26:50 PM PDT 24 |
45700536 ps |
| T117 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.438996830 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
314282447 ps |
| T970 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2910424392 |
|
|
Aug 14 04:26:46 PM PDT 24 |
Aug 14 04:26:47 PM PDT 24 |
18902469 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4155168865 |
|
|
Aug 14 04:26:47 PM PDT 24 |
Aug 14 04:26:50 PM PDT 24 |
33675848 ps |
| T110 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1418749101 |
|
|
Aug 14 04:26:45 PM PDT 24 |
Aug 14 04:26:46 PM PDT 24 |
21780392 ps |
| T972 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.788933526 |
|
|
Aug 14 04:26:44 PM PDT 24 |
Aug 14 04:26:46 PM PDT 24 |
86910487 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1962729708 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
31584445 ps |
| T974 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2095899572 |
|
|
Aug 14 04:26:52 PM PDT 24 |
Aug 14 04:26:53 PM PDT 24 |
10493601 ps |
| T132 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3286150455 |
|
|
Aug 14 04:26:41 PM PDT 24 |
Aug 14 04:26:43 PM PDT 24 |
185950846 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1138741960 |
|
|
Aug 14 04:26:30 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
25176464 ps |
| T112 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.268021666 |
|
|
Aug 14 04:26:51 PM PDT 24 |
Aug 14 04:26:52 PM PDT 24 |
59702193 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1389807438 |
|
|
Aug 14 04:26:30 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
27231422 ps |
| T142 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2105950935 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:31 PM PDT 24 |
697938588 ps |
| T977 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.428778407 |
|
|
Aug 14 04:26:49 PM PDT 24 |
Aug 14 04:26:50 PM PDT 24 |
90854997 ps |
| T113 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2965691334 |
|
|
Aug 14 04:26:49 PM PDT 24 |
Aug 14 04:26:53 PM PDT 24 |
3575490903 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3060468072 |
|
|
Aug 14 04:26:24 PM PDT 24 |
Aug 14 04:26:26 PM PDT 24 |
534604646 ps |
| T978 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3001343400 |
|
|
Aug 14 04:26:37 PM PDT 24 |
Aug 14 04:26:38 PM PDT 24 |
18249676 ps |
| T979 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.435907654 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
822803685 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3036945924 |
|
|
Aug 14 04:26:31 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
18266038 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1383425393 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:28 PM PDT 24 |
31391515 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2006641988 |
|
|
Aug 14 04:26:37 PM PDT 24 |
Aug 14 04:26:39 PM PDT 24 |
487974631 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2599612962 |
|
|
Aug 14 04:26:42 PM PDT 24 |
Aug 14 04:26:42 PM PDT 24 |
59363411 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2847453376 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:33 PM PDT 24 |
37783628 ps |
| T115 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3075449887 |
|
|
Aug 14 04:26:29 PM PDT 24 |
Aug 14 04:26:31 PM PDT 24 |
367764105 ps |
| T985 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4156345087 |
|
|
Aug 14 04:26:43 PM PDT 24 |
Aug 14 04:26:46 PM PDT 24 |
1639042489 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3894098585 |
|
|
Aug 14 04:27:00 PM PDT 24 |
Aug 14 04:27:02 PM PDT 24 |
44553258 ps |
| T987 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3900648527 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:31 PM PDT 24 |
722529945 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1609911674 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:29 PM PDT 24 |
13383563 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2461698452 |
|
|
Aug 14 04:26:38 PM PDT 24 |
Aug 14 04:26:39 PM PDT 24 |
17793413 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2708440227 |
|
|
Aug 14 04:26:56 PM PDT 24 |
Aug 14 04:26:59 PM PDT 24 |
106159748 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2141270930 |
|
|
Aug 14 04:26:58 PM PDT 24 |
Aug 14 04:26:59 PM PDT 24 |
11505584 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3758203504 |
|
|
Aug 14 04:26:48 PM PDT 24 |
Aug 14 04:26:50 PM PDT 24 |
879070531 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3121970761 |
|
|
Aug 14 04:26:32 PM PDT 24 |
Aug 14 04:26:32 PM PDT 24 |
22809619 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2154781814 |
|
|
Aug 14 04:26:46 PM PDT 24 |
Aug 14 04:26:47 PM PDT 24 |
71468453 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1095987811 |
|
|
Aug 14 04:26:30 PM PDT 24 |
Aug 14 04:26:31 PM PDT 24 |
126324536 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3008931897 |
|
|
Aug 14 04:26:53 PM PDT 24 |
Aug 14 04:26:54 PM PDT 24 |
469671419 ps |
| T997 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2066315439 |
|
|
Aug 14 04:26:45 PM PDT 24 |
Aug 14 04:26:46 PM PDT 24 |
31588225 ps |
| T141 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2737762345 |
|
|
Aug 14 04:26:27 PM PDT 24 |
Aug 14 04:26:29 PM PDT 24 |
225386523 ps |
| T998 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1939602935 |
|
|
Aug 14 04:26:31 PM PDT 24 |
Aug 14 04:26:33 PM PDT 24 |
86137319 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3836604186 |
|
|
Aug 14 04:27:01 PM PDT 24 |
Aug 14 04:27:02 PM PDT 24 |
25145656 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2923880087 |
|
|
Aug 14 04:26:48 PM PDT 24 |
Aug 14 04:26:50 PM PDT 24 |
851135141 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2212668618 |
|
|
Aug 14 04:26:28 PM PDT 24 |
Aug 14 04:26:30 PM PDT 24 |
46269456 ps |