Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	155980358	1			T1	271272		T2	1844		T4	331764
instr_valid_dis	117946484	1			T1	198402		T2	1844		T4	331764
instr_en	26326432	1			T1	72748		T15	97548		T20	703686

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11677290	1			T1	54484		T15	40340		T16	130522
sram_ifetch_valid_disable	120395144	1			T1	181848		T2	1844		T4	331764
sram_ifetch_enable	23907924	1			T1	34940		T15	281300		T16	151142

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	155980358	1			T1	271272		T2	1844		T4	331764
hw_debug_en_valid_off	118639059	1			T1	143022		T2	1844		T4	331764
hw_debug_en_on	23993623	1			T1	95036		T15	168016		T16	28702

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	120395144	1			T1	181848		T2	1844		T4	331764
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	104925198	1			T1	115934		T2	1844		T4	331764
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10682256	1			T1	65914		T15	57018		T20	90434
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3587178	1			T16	130522		T149	4472		T20	40066
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1321330	1			T16	130522		T17	3450		T78	7458
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1522314	1			T20	19056		T150	20000		T63	18686
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5081118	1			T1	43502		T20	440964		T45	24618
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1696984	1			T1	43502		T45	24618		T150	13122
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2735996	1			T20	420964		T77	13602		T79	14124
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9651798	1			T1	23550		T15	50548		T16	6666
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3594998	1			T16	6666		T20	63954		T45	48980
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4267492	1			T1	23550		T15	16300		T20	42874

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10171858	1			T1	6834		T15	40530		T20	159402
lc_exec_en	9260707	1			T1	27984		T15	117468		T16	22036
valid_exec_dis	114244873	1			T1	164172		T2	1844		T4	331764
invalid_exec_dis	35585214	1			T1	89424		T15	321640		T16	281664