Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	46615724	1			T1	60611		T2	54		T4	30217
triple_byte_access	2637673	1			T1	1138		T2	120		T4	27040
halfword_access	3958141	1			T1	1865		T2	192		T4	40649
byte_access	5279730	1			T1	2487		T2	366		T4	54361
zero_access	1329327	1			T1	625		T2	190		T4	13615

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29855010

1

T1

33323

T2

339

T4

83047

auto[1]

29965585

1

T1

33403

T2

583

T4

82835

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	23257967	1			T1	30299		T2	2		T4	15178
auto[0]	triple_byte_access	1315383	1			T1	564		T2	16		T4	13485
auto[0]	halfword_access	1974234	1			T1	912		T2	37		T4	20235
auto[0]	byte_access	2639496	1			T1	1235		T2	152		T4	27311
auto[0]	zero_access	667930	1			T1	313		T2	132		T4	6838
auto[1]	word_access	23357757	1			T1	30312		T2	52		T4	15039
auto[1]	triple_byte_access	1322290	1			T1	574		T2	104		T4	13555
auto[1]	halfword_access	1983907	1			T1	953		T2	155		T4	20414
auto[1]	byte_access	2640234	1			T1	1252		T2	214		T4	27050
auto[1]	zero_access	661397	1			T1	312		T2	58		T4	6777