| T802 |
/workspace/coverage/default/30.sram_ctrl_stress_all.980163288 |
|
|
Aug 18 05:54:52 PM PDT 24 |
Aug 18 06:26:18 PM PDT 24 |
73176764470 ps |
| T803 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3183934532 |
|
|
Aug 18 05:55:00 PM PDT 24 |
Aug 18 05:55:10 PM PDT 24 |
1153519874 ps |
| T804 |
/workspace/coverage/default/11.sram_ctrl_executable.2546462679 |
|
|
Aug 18 05:53:34 PM PDT 24 |
Aug 18 06:07:16 PM PDT 24 |
13073145771 ps |
| T805 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1876312369 |
|
|
Aug 18 05:52:57 PM PDT 24 |
Aug 18 06:04:48 PM PDT 24 |
5543131950 ps |
| T124 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1148336769 |
|
|
Aug 18 05:53:37 PM PDT 24 |
Aug 18 05:54:45 PM PDT 24 |
4213672463 ps |
| T806 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3976949945 |
|
|
Aug 18 05:52:58 PM PDT 24 |
Aug 18 06:04:16 PM PDT 24 |
12002259258 ps |
| T807 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3313024645 |
|
|
Aug 18 05:53:31 PM PDT 24 |
Aug 18 05:54:09 PM PDT 24 |
106030466 ps |
| T808 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.429322791 |
|
|
Aug 18 05:53:41 PM PDT 24 |
Aug 18 06:07:22 PM PDT 24 |
12751774603 ps |
| T809 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3908957236 |
|
|
Aug 18 05:52:56 PM PDT 24 |
Aug 18 05:53:01 PM PDT 24 |
51694256 ps |
| T810 |
/workspace/coverage/default/36.sram_ctrl_bijection.2944500489 |
|
|
Aug 18 05:55:07 PM PDT 24 |
Aug 18 05:55:39 PM PDT 24 |
5460974008 ps |
| T811 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.441462007 |
|
|
Aug 18 05:54:45 PM PDT 24 |
Aug 18 05:58:45 PM PDT 24 |
840126336 ps |
| T812 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1417566613 |
|
|
Aug 18 05:53:24 PM PDT 24 |
Aug 18 05:53:30 PM PDT 24 |
337495675 ps |
| T813 |
/workspace/coverage/default/31.sram_ctrl_partial_access.740056213 |
|
|
Aug 18 05:54:53 PM PDT 24 |
Aug 18 05:55:07 PM PDT 24 |
272761805 ps |
| T814 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2189279136 |
|
|
Aug 18 05:53:14 PM PDT 24 |
Aug 18 05:54:45 PM PDT 24 |
570467594 ps |
| T815 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1733866677 |
|
|
Aug 18 05:54:07 PM PDT 24 |
Aug 18 05:54:11 PM PDT 24 |
216201851 ps |
| T816 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.726813323 |
|
|
Aug 18 05:53:24 PM PDT 24 |
Aug 18 05:53:29 PM PDT 24 |
700349563 ps |
| T817 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2477333717 |
|
|
Aug 18 05:55:22 PM PDT 24 |
Aug 18 05:55:23 PM PDT 24 |
117661476 ps |
| T818 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1911975781 |
|
|
Aug 18 05:55:57 PM PDT 24 |
Aug 18 05:56:01 PM PDT 24 |
293423285 ps |
| T819 |
/workspace/coverage/default/35.sram_ctrl_executable.1433626269 |
|
|
Aug 18 05:55:09 PM PDT 24 |
Aug 18 06:15:19 PM PDT 24 |
14139444663 ps |
| T820 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2896475690 |
|
|
Aug 18 05:54:45 PM PDT 24 |
Aug 18 05:54:48 PM PDT 24 |
202313538 ps |
| T125 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2010457646 |
|
|
Aug 18 05:55:38 PM PDT 24 |
Aug 18 05:56:03 PM PDT 24 |
4161376212 ps |
| T821 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2045296585 |
|
|
Aug 18 05:54:14 PM PDT 24 |
Aug 18 06:02:59 PM PDT 24 |
7572927787 ps |
| T822 |
/workspace/coverage/default/0.sram_ctrl_partial_access.2057607868 |
|
|
Aug 18 05:52:57 PM PDT 24 |
Aug 18 05:53:39 PM PDT 24 |
1268272099 ps |
| T823 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3699734982 |
|
|
Aug 18 05:54:12 PM PDT 24 |
Aug 18 05:58:06 PM PDT 24 |
2467840857 ps |
| T824 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2202457963 |
|
|
Aug 18 05:54:40 PM PDT 24 |
Aug 18 05:55:11 PM PDT 24 |
354285432 ps |
| T825 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.995392504 |
|
|
Aug 18 05:54:20 PM PDT 24 |
Aug 18 06:00:05 PM PDT 24 |
10440988643 ps |
| T826 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1791614937 |
|
|
Aug 18 05:53:45 PM PDT 24 |
Aug 18 05:55:27 PM PDT 24 |
817735374 ps |
| T827 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.674689653 |
|
|
Aug 18 05:53:24 PM PDT 24 |
Aug 18 06:10:25 PM PDT 24 |
29513825482 ps |
| T828 |
/workspace/coverage/default/15.sram_ctrl_bijection.2159140683 |
|
|
Aug 18 05:53:44 PM PDT 24 |
Aug 18 05:54:14 PM PDT 24 |
439691227 ps |
| T829 |
/workspace/coverage/default/18.sram_ctrl_partial_access.3435367516 |
|
|
Aug 18 05:54:00 PM PDT 24 |
Aug 18 05:54:06 PM PDT 24 |
379315995 ps |
| T830 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.306688863 |
|
|
Aug 18 05:53:23 PM PDT 24 |
Aug 18 06:07:36 PM PDT 24 |
3638750667 ps |
| T831 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2982303873 |
|
|
Aug 18 05:54:21 PM PDT 24 |
Aug 18 05:59:03 PM PDT 24 |
2963543127 ps |
| T832 |
/workspace/coverage/default/17.sram_ctrl_regwen.794424492 |
|
|
Aug 18 05:53:57 PM PDT 24 |
Aug 18 06:05:32 PM PDT 24 |
2198346344 ps |
| T833 |
/workspace/coverage/default/0.sram_ctrl_regwen.670175355 |
|
|
Aug 18 05:52:57 PM PDT 24 |
Aug 18 06:07:17 PM PDT 24 |
8635674840 ps |
| T834 |
/workspace/coverage/default/12.sram_ctrl_executable.779206563 |
|
|
Aug 18 05:53:38 PM PDT 24 |
Aug 18 06:02:50 PM PDT 24 |
13400277747 ps |
| T835 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1788199635 |
|
|
Aug 18 05:54:35 PM PDT 24 |
Aug 18 05:54:36 PM PDT 24 |
31041754 ps |
| T836 |
/workspace/coverage/default/35.sram_ctrl_smoke.4224358274 |
|
|
Aug 18 05:55:05 PM PDT 24 |
Aug 18 05:55:19 PM PDT 24 |
444560732 ps |
| T837 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.3840454789 |
|
|
Aug 18 05:55:09 PM PDT 24 |
Aug 18 06:06:40 PM PDT 24 |
2201023877 ps |
| T838 |
/workspace/coverage/default/8.sram_ctrl_alert_test.4190361946 |
|
|
Aug 18 05:53:24 PM PDT 24 |
Aug 18 05:53:25 PM PDT 24 |
14708271 ps |
| T839 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1335562581 |
|
|
Aug 18 05:53:21 PM PDT 24 |
Aug 18 05:56:58 PM PDT 24 |
2379873823 ps |
| T840 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.2929059662 |
|
|
Aug 18 05:53:58 PM PDT 24 |
Aug 18 05:54:09 PM PDT 24 |
3436053852 ps |
| T841 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3030832759 |
|
|
Aug 18 05:55:01 PM PDT 24 |
Aug 18 05:55:04 PM PDT 24 |
523408892 ps |
| T842 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.990459481 |
|
|
Aug 18 05:53:15 PM PDT 24 |
Aug 18 05:53:18 PM PDT 24 |
51401784 ps |
| T843 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1901966884 |
|
|
Aug 18 05:55:17 PM PDT 24 |
Aug 18 06:00:01 PM PDT 24 |
19729343753 ps |
| T844 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.776906367 |
|
|
Aug 18 05:53:07 PM PDT 24 |
Aug 18 05:53:09 PM PDT 24 |
43972682 ps |
| T845 |
/workspace/coverage/default/0.sram_ctrl_stress_all.614424065 |
|
|
Aug 18 05:52:59 PM PDT 24 |
Aug 18 06:29:45 PM PDT 24 |
7536835982 ps |
| T846 |
/workspace/coverage/default/3.sram_ctrl_bijection.3349211760 |
|
|
Aug 18 05:53:05 PM PDT 24 |
Aug 18 05:53:26 PM PDT 24 |
1405196693 ps |
| T847 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.959704102 |
|
|
Aug 18 05:54:09 PM PDT 24 |
Aug 18 06:01:27 PM PDT 24 |
6292870778 ps |
| T848 |
/workspace/coverage/default/9.sram_ctrl_regwen.2000197740 |
|
|
Aug 18 05:53:33 PM PDT 24 |
Aug 18 06:02:58 PM PDT 24 |
12826197212 ps |
| T849 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4277479127 |
|
|
Aug 18 05:53:34 PM PDT 24 |
Aug 18 05:54:35 PM PDT 24 |
7102727652 ps |
| T850 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1635425512 |
|
|
Aug 18 05:55:14 PM PDT 24 |
Aug 18 05:55:20 PM PDT 24 |
301609893 ps |
| T851 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3625146739 |
|
|
Aug 18 05:53:37 PM PDT 24 |
Aug 18 05:59:16 PM PDT 24 |
3189484098 ps |
| T852 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4199200662 |
|
|
Aug 18 05:53:33 PM PDT 24 |
Aug 18 05:53:38 PM PDT 24 |
157160692 ps |
| T853 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.456656443 |
|
|
Aug 18 05:53:05 PM PDT 24 |
Aug 18 05:54:52 PM PDT 24 |
173549920 ps |
| T854 |
/workspace/coverage/default/34.sram_ctrl_executable.3672428146 |
|
|
Aug 18 05:54:59 PM PDT 24 |
Aug 18 06:05:58 PM PDT 24 |
4369365279 ps |
| T855 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.727568091 |
|
|
Aug 18 05:55:37 PM PDT 24 |
Aug 18 05:55:42 PM PDT 24 |
129467790 ps |
| T856 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1870730688 |
|
|
Aug 18 05:56:21 PM PDT 24 |
Aug 18 05:59:37 PM PDT 24 |
3937156494 ps |
| T857 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3539291614 |
|
|
Aug 18 05:53:46 PM PDT 24 |
Aug 18 05:53:49 PM PDT 24 |
328513208 ps |
| T858 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.22285012 |
|
|
Aug 18 05:56:16 PM PDT 24 |
Aug 18 06:00:04 PM PDT 24 |
11109953764 ps |
| T859 |
/workspace/coverage/default/41.sram_ctrl_smoke.1353223476 |
|
|
Aug 18 05:55:37 PM PDT 24 |
Aug 18 05:56:35 PM PDT 24 |
224157823 ps |
| T860 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3135281955 |
|
|
Aug 18 05:56:23 PM PDT 24 |
Aug 18 05:56:29 PM PDT 24 |
237325600 ps |
| T861 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.561885727 |
|
|
Aug 18 05:53:06 PM PDT 24 |
Aug 18 05:53:08 PM PDT 24 |
136247399 ps |
| T862 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.320721922 |
|
|
Aug 18 05:53:31 PM PDT 24 |
Aug 18 05:57:20 PM PDT 24 |
2352378254 ps |
| T863 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4198955636 |
|
|
Aug 18 05:52:58 PM PDT 24 |
Aug 18 06:00:12 PM PDT 24 |
17653185781 ps |
| T864 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2737874373 |
|
|
Aug 18 05:53:39 PM PDT 24 |
Aug 18 05:53:45 PM PDT 24 |
251389019 ps |
| T865 |
/workspace/coverage/default/14.sram_ctrl_bijection.3548259454 |
|
|
Aug 18 05:53:43 PM PDT 24 |
Aug 18 05:54:50 PM PDT 24 |
1080908094 ps |
| T866 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.4127149921 |
|
|
Aug 18 05:54:31 PM PDT 24 |
Aug 18 05:56:21 PM PDT 24 |
733350427 ps |
| T867 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1355952810 |
|
|
Aug 18 05:53:44 PM PDT 24 |
Aug 18 05:54:03 PM PDT 24 |
2116125010 ps |
| T868 |
/workspace/coverage/default/36.sram_ctrl_smoke.908417050 |
|
|
Aug 18 05:55:09 PM PDT 24 |
Aug 18 05:57:06 PM PDT 24 |
136561869 ps |
| T869 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1526109780 |
|
|
Aug 18 05:54:12 PM PDT 24 |
Aug 18 06:12:12 PM PDT 24 |
14592023836 ps |
| T870 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1464722190 |
|
|
Aug 18 05:53:13 PM PDT 24 |
Aug 18 05:54:12 PM PDT 24 |
15550295616 ps |
| T871 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3793817792 |
|
|
Aug 18 05:54:31 PM PDT 24 |
Aug 18 05:55:17 PM PDT 24 |
442058961 ps |
| T872 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2410997646 |
|
|
Aug 18 05:54:51 PM PDT 24 |
Aug 18 06:02:02 PM PDT 24 |
16215648973 ps |
| T873 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1835410325 |
|
|
Aug 18 05:56:24 PM PDT 24 |
Aug 18 05:56:25 PM PDT 24 |
16146355 ps |
| T874 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.4266870367 |
|
|
Aug 18 05:55:37 PM PDT 24 |
Aug 18 05:55:44 PM PDT 24 |
490937063 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.3244553673 |
|
|
Aug 18 05:54:41 PM PDT 24 |
Aug 18 05:55:54 PM PDT 24 |
167776900 ps |
| T876 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3479439435 |
|
|
Aug 18 05:53:13 PM PDT 24 |
Aug 18 05:58:11 PM PDT 24 |
3296226756 ps |
| T877 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2573534760 |
|
|
Aug 18 05:53:38 PM PDT 24 |
Aug 18 05:53:39 PM PDT 24 |
90436962 ps |
| T878 |
/workspace/coverage/default/29.sram_ctrl_smoke.460590499 |
|
|
Aug 18 05:54:46 PM PDT 24 |
Aug 18 05:55:38 PM PDT 24 |
1222185926 ps |
| T879 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2276346813 |
|
|
Aug 18 05:53:58 PM PDT 24 |
Aug 18 05:53:59 PM PDT 24 |
78654708 ps |
| T880 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1875993633 |
|
|
Aug 18 05:54:01 PM PDT 24 |
Aug 18 06:05:41 PM PDT 24 |
41660594727 ps |
| T881 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3363030201 |
|
|
Aug 18 05:55:50 PM PDT 24 |
Aug 18 05:55:56 PM PDT 24 |
1694981681 ps |
| T882 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.142465005 |
|
|
Aug 18 05:55:01 PM PDT 24 |
Aug 18 05:57:18 PM PDT 24 |
148959821 ps |
| T883 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3619673310 |
|
|
Aug 18 05:55:09 PM PDT 24 |
Aug 18 05:55:12 PM PDT 24 |
708082821 ps |
| T884 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2380945489 |
|
|
Aug 18 05:54:19 PM PDT 24 |
Aug 18 05:57:23 PM PDT 24 |
6490528079 ps |
| T885 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3214492366 |
|
|
Aug 18 05:54:23 PM PDT 24 |
Aug 18 05:55:38 PM PDT 24 |
232096127 ps |
| T886 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.269750420 |
|
|
Aug 18 05:54:54 PM PDT 24 |
Aug 18 05:57:58 PM PDT 24 |
8809305703 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2326621974 |
|
|
Aug 18 05:55:03 PM PDT 24 |
Aug 18 06:47:21 PM PDT 24 |
44055444435 ps |
| T888 |
/workspace/coverage/default/6.sram_ctrl_executable.2957973197 |
|
|
Aug 18 05:53:13 PM PDT 24 |
Aug 18 06:14:48 PM PDT 24 |
13622163741 ps |
| T889 |
/workspace/coverage/default/38.sram_ctrl_executable.689822493 |
|
|
Aug 18 05:55:23 PM PDT 24 |
Aug 18 06:02:58 PM PDT 24 |
47184645625 ps |
| T890 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3748683148 |
|
|
Aug 18 05:54:40 PM PDT 24 |
Aug 18 06:15:20 PM PDT 24 |
4084174480 ps |
| T891 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3722694012 |
|
|
Aug 18 05:53:05 PM PDT 24 |
Aug 18 06:03:52 PM PDT 24 |
9177096123 ps |
| T892 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.387827187 |
|
|
Aug 18 05:53:00 PM PDT 24 |
Aug 18 05:59:14 PM PDT 24 |
67876355225 ps |
| T893 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.4087092829 |
|
|
Aug 18 05:53:31 PM PDT 24 |
Aug 18 05:53:43 PM PDT 24 |
658389928 ps |
| T894 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1581418744 |
|
|
Aug 18 05:54:58 PM PDT 24 |
Aug 18 05:55:06 PM PDT 24 |
136622473 ps |
| T895 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2714081721 |
|
|
Aug 18 05:54:06 PM PDT 24 |
Aug 18 05:54:37 PM PDT 24 |
1191959576 ps |
| T896 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3743230214 |
|
|
Aug 18 05:53:45 PM PDT 24 |
Aug 18 05:53:47 PM PDT 24 |
322912753 ps |
| T897 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3270189001 |
|
|
Aug 18 05:56:33 PM PDT 24 |
Aug 18 06:09:47 PM PDT 24 |
12656711741 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1961902785 |
|
|
Aug 18 05:54:32 PM PDT 24 |
Aug 18 05:54:46 PM PDT 24 |
1089672658 ps |
| T899 |
/workspace/coverage/default/39.sram_ctrl_executable.3901944710 |
|
|
Aug 18 05:55:31 PM PDT 24 |
Aug 18 06:03:30 PM PDT 24 |
1537408717 ps |
| T900 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1004706537 |
|
|
Aug 18 05:53:16 PM PDT 24 |
Aug 18 05:57:07 PM PDT 24 |
338902924 ps |
| T901 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.421460885 |
|
|
Aug 18 05:55:30 PM PDT 24 |
Aug 18 06:27:25 PM PDT 24 |
22906943583 ps |
| T902 |
/workspace/coverage/default/8.sram_ctrl_partial_access.398470567 |
|
|
Aug 18 05:53:23 PM PDT 24 |
Aug 18 05:53:33 PM PDT 24 |
1222529729 ps |
| T903 |
/workspace/coverage/default/11.sram_ctrl_smoke.3292655589 |
|
|
Aug 18 05:53:34 PM PDT 24 |
Aug 18 05:53:44 PM PDT 24 |
162478745 ps |
| T904 |
/workspace/coverage/default/48.sram_ctrl_regwen.469779773 |
|
|
Aug 18 05:56:25 PM PDT 24 |
Aug 18 06:14:17 PM PDT 24 |
41264031724 ps |
| T905 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.909335310 |
|
|
Aug 18 05:53:07 PM PDT 24 |
Aug 18 05:53:10 PM PDT 24 |
203523803 ps |
| T906 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2300791575 |
|
|
Aug 18 05:54:22 PM PDT 24 |
Aug 18 05:54:23 PM PDT 24 |
129460855 ps |
| T907 |
/workspace/coverage/default/25.sram_ctrl_executable.311066891 |
|
|
Aug 18 05:54:22 PM PDT 24 |
Aug 18 06:13:53 PM PDT 24 |
29882831311 ps |
| T908 |
/workspace/coverage/default/4.sram_ctrl_executable.4166450841 |
|
|
Aug 18 05:53:11 PM PDT 24 |
Aug 18 06:02:57 PM PDT 24 |
5122375521 ps |
| T909 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3567889696 |
|
|
Aug 18 05:54:23 PM PDT 24 |
Aug 18 05:54:34 PM PDT 24 |
1620828670 ps |
| T910 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1529771965 |
|
|
Aug 18 05:53:33 PM PDT 24 |
Aug 18 05:53:36 PM PDT 24 |
176385158 ps |
| T911 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3824708697 |
|
|
Aug 18 05:55:46 PM PDT 24 |
Aug 18 05:55:53 PM PDT 24 |
664309548 ps |
| T912 |
/workspace/coverage/default/19.sram_ctrl_bijection.2647671079 |
|
|
Aug 18 05:53:59 PM PDT 24 |
Aug 18 05:54:45 PM PDT 24 |
2941689712 ps |
| T913 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3919208297 |
|
|
Aug 18 05:53:32 PM PDT 24 |
Aug 18 05:59:03 PM PDT 24 |
16333779092 ps |
| T914 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.2407130128 |
|
|
Aug 18 05:55:37 PM PDT 24 |
Aug 18 06:15:52 PM PDT 24 |
15105136522 ps |
| T915 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3621945497 |
|
|
Aug 18 05:53:13 PM PDT 24 |
Aug 18 05:53:47 PM PDT 24 |
461184226 ps |
| T916 |
/workspace/coverage/default/6.sram_ctrl_smoke.1519210543 |
|
|
Aug 18 05:53:14 PM PDT 24 |
Aug 18 05:55:02 PM PDT 24 |
1429332612 ps |
| T917 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2458029505 |
|
|
Aug 18 05:54:14 PM PDT 24 |
Aug 18 06:00:47 PM PDT 24 |
95519685263 ps |
| T918 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3363141777 |
|
|
Aug 18 05:53:09 PM PDT 24 |
Aug 18 05:53:14 PM PDT 24 |
130598277 ps |
| T919 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1452342191 |
|
|
Aug 18 05:54:58 PM PDT 24 |
Aug 18 05:54:59 PM PDT 24 |
44014768 ps |
| T920 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2369350939 |
|
|
Aug 18 05:56:16 PM PDT 24 |
Aug 18 05:56:30 PM PDT 24 |
257537619 ps |
| T921 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2958927900 |
|
|
Aug 18 05:56:04 PM PDT 24 |
Aug 18 05:56:41 PM PDT 24 |
1112409962 ps |
| T922 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2638678937 |
|
|
Aug 18 05:56:25 PM PDT 24 |
Aug 18 05:58:13 PM PDT 24 |
126228858 ps |
| T923 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2916296154 |
|
|
Aug 18 05:55:31 PM PDT 24 |
Aug 18 05:55:36 PM PDT 24 |
283231523 ps |
| T924 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1549122788 |
|
|
Aug 18 05:54:34 PM PDT 24 |
Aug 18 05:54:35 PM PDT 24 |
14058091 ps |
| T925 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.1403847922 |
|
|
Aug 18 05:53:07 PM PDT 24 |
Aug 18 05:53:19 PM PDT 24 |
681652524 ps |
| T926 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4096399156 |
|
|
Aug 18 05:53:04 PM PDT 24 |
Aug 18 05:53:18 PM PDT 24 |
657686990 ps |
| T927 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1839423664 |
|
|
Aug 18 05:56:23 PM PDT 24 |
Aug 18 05:57:31 PM PDT 24 |
130526022 ps |
| T928 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1896185837 |
|
|
Aug 18 05:55:00 PM PDT 24 |
Aug 18 05:55:11 PM PDT 24 |
2709023563 ps |
| T929 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3448557672 |
|
|
Aug 18 05:56:31 PM PDT 24 |
Aug 18 06:41:53 PM PDT 24 |
9220569421 ps |
| T930 |
/workspace/coverage/default/36.sram_ctrl_alert_test.4218152161 |
|
|
Aug 18 05:55:18 PM PDT 24 |
Aug 18 05:55:19 PM PDT 24 |
14045289 ps |
| T931 |
/workspace/coverage/default/34.sram_ctrl_bijection.231797064 |
|
|
Aug 18 05:55:01 PM PDT 24 |
Aug 18 05:55:37 PM PDT 24 |
1605398002 ps |
| T932 |
/workspace/coverage/default/46.sram_ctrl_alert_test.352175073 |
|
|
Aug 18 05:56:16 PM PDT 24 |
Aug 18 05:56:16 PM PDT 24 |
23550359 ps |
| T933 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.3266442814 |
|
|
Aug 18 05:56:24 PM PDT 24 |
Aug 18 05:56:29 PM PDT 24 |
434026789 ps |
| T934 |
/workspace/coverage/default/27.sram_ctrl_smoke.486552985 |
|
|
Aug 18 05:54:32 PM PDT 24 |
Aug 18 05:54:38 PM PDT 24 |
99872018 ps |
| T935 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.392585881 |
|
|
Aug 18 05:54:13 PM PDT 24 |
Aug 18 05:54:13 PM PDT 24 |
107606694 ps |
| T936 |
/workspace/coverage/default/43.sram_ctrl_alert_test.174422112 |
|
|
Aug 18 05:55:57 PM PDT 24 |
Aug 18 05:55:58 PM PDT 24 |
12948041 ps |
| T937 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2867254954 |
|
|
Aug 18 05:56:22 PM PDT 24 |
Aug 18 06:07:53 PM PDT 24 |
63408043410 ps |
| T938 |
/workspace/coverage/default/29.sram_ctrl_bijection.3320863667 |
|
|
Aug 18 05:54:42 PM PDT 24 |
Aug 18 05:55:24 PM PDT 24 |
5323507069 ps |
| T939 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3463461973 |
|
|
Aug 18 05:55:25 PM PDT 24 |
Aug 18 07:01:57 PM PDT 24 |
43751537487 ps |
| T940 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2104801664 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
40653019 ps |
| T941 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.950712424 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
154648881 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.415456924 |
|
|
Aug 18 05:22:25 PM PDT 24 |
Aug 18 05:22:27 PM PDT 24 |
424987215 ps |
| T942 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1485263893 |
|
|
Aug 18 05:22:44 PM PDT 24 |
Aug 18 05:22:48 PM PDT 24 |
412410267 ps |
| T66 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3166149905 |
|
|
Aug 18 05:22:28 PM PDT 24 |
Aug 18 05:22:28 PM PDT 24 |
16425522 ps |
| T67 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.41547370 |
|
|
Aug 18 05:22:18 PM PDT 24 |
Aug 18 05:22:20 PM PDT 24 |
2391424361 ps |
| T943 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1235669100 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:49 PM PDT 24 |
143609117 ps |
| T117 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.861494293 |
|
|
Aug 18 05:22:00 PM PDT 24 |
Aug 18 05:22:00 PM PDT 24 |
47200932 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3034649402 |
|
|
Aug 18 05:22:26 PM PDT 24 |
Aug 18 05:22:29 PM PDT 24 |
62943424 ps |
| T106 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1579624696 |
|
|
Aug 18 05:22:48 PM PDT 24 |
Aug 18 05:22:49 PM PDT 24 |
73669741 ps |
| T80 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2436768738 |
|
|
Aug 18 05:22:01 PM PDT 24 |
Aug 18 05:22:02 PM PDT 24 |
37598722 ps |
| T147 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3334154499 |
|
|
Aug 18 05:22:06 PM PDT 24 |
Aug 18 05:22:09 PM PDT 24 |
122388517 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.717696027 |
|
|
Aug 18 05:22:36 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
116002288 ps |
| T81 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2073673725 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:11 PM PDT 24 |
297133505 ps |
| T946 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.820007083 |
|
|
Aug 18 05:22:36 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
71601665 ps |
| T60 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.399203250 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
123377218 ps |
| T947 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1319855792 |
|
|
Aug 18 05:21:58 PM PDT 24 |
Aug 18 05:21:59 PM PDT 24 |
14931708 ps |
| T107 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3345255011 |
|
|
Aug 18 05:22:27 PM PDT 24 |
Aug 18 05:22:28 PM PDT 24 |
80209970 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1011095878 |
|
|
Aug 18 05:22:47 PM PDT 24 |
Aug 18 05:22:48 PM PDT 24 |
267596276 ps |
| T949 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4170976185 |
|
|
Aug 18 05:22:38 PM PDT 24 |
Aug 18 05:22:38 PM PDT 24 |
43565297 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1417318244 |
|
|
Aug 18 05:22:05 PM PDT 24 |
Aug 18 05:22:05 PM PDT 24 |
17242101 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.97641904 |
|
|
Aug 18 05:22:27 PM PDT 24 |
Aug 18 05:22:28 PM PDT 24 |
90524457 ps |
| T118 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3138651461 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:10 PM PDT 24 |
13658520 ps |
| T108 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2736265026 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
31501764 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1828278531 |
|
|
Aug 18 05:22:29 PM PDT 24 |
Aug 18 05:22:30 PM PDT 24 |
55865649 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2815872553 |
|
|
Aug 18 05:21:49 PM PDT 24 |
Aug 18 05:21:53 PM PDT 24 |
140869025 ps |
| T82 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2238989978 |
|
|
Aug 18 05:21:59 PM PDT 24 |
Aug 18 05:21:59 PM PDT 24 |
10988477 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.139101959 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:10 PM PDT 24 |
16957622 ps |
| T954 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3890334796 |
|
|
Aug 18 05:22:47 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
46388327 ps |
| T109 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3453540456 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:36 PM PDT 24 |
35820145 ps |
| T110 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.312799668 |
|
|
Aug 18 05:22:51 PM PDT 24 |
Aug 18 05:22:51 PM PDT 24 |
21581543 ps |
| T84 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1951150735 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
196597924 ps |
| T955 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1205400959 |
|
|
Aug 18 05:22:56 PM PDT 24 |
Aug 18 05:22:57 PM PDT 24 |
23467147 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4129703431 |
|
|
Aug 18 05:22:18 PM PDT 24 |
Aug 18 05:22:21 PM PDT 24 |
714110599 ps |
| T957 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2040964022 |
|
|
Aug 18 05:22:19 PM PDT 24 |
Aug 18 05:22:23 PM PDT 24 |
199670501 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4292401719 |
|
|
Aug 18 05:21:58 PM PDT 24 |
Aug 18 05:22:00 PM PDT 24 |
125879329 ps |
| T959 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3312053896 |
|
|
Aug 18 05:22:17 PM PDT 24 |
Aug 18 05:22:18 PM PDT 24 |
52132433 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1394395355 |
|
|
Aug 18 05:22:08 PM PDT 24 |
Aug 18 05:22:10 PM PDT 24 |
29395248 ps |
| T61 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3806509325 |
|
|
Aug 18 05:22:36 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
344156715 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2872729397 |
|
|
Aug 18 05:21:58 PM PDT 24 |
Aug 18 05:21:59 PM PDT 24 |
31913435 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2048998969 |
|
|
Aug 18 05:22:10 PM PDT 24 |
Aug 18 05:22:11 PM PDT 24 |
17198816 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3178654055 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:13 PM PDT 24 |
424529365 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2170011 |
|
|
Aug 18 05:22:17 PM PDT 24 |
Aug 18 05:22:18 PM PDT 24 |
44825701 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2160122273 |
|
|
Aug 18 05:22:19 PM PDT 24 |
Aug 18 05:22:19 PM PDT 24 |
20896702 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3285934355 |
|
|
Aug 18 05:22:19 PM PDT 24 |
Aug 18 05:22:19 PM PDT 24 |
15944917 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3012689773 |
|
|
Aug 18 05:22:27 PM PDT 24 |
Aug 18 05:22:28 PM PDT 24 |
20154807 ps |
| T964 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1977233967 |
|
|
Aug 18 05:22:57 PM PDT 24 |
Aug 18 05:23:01 PM PDT 24 |
77540588 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2633832939 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
313669230 ps |
| T966 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2717938113 |
|
|
Aug 18 05:22:38 PM PDT 24 |
Aug 18 05:22:39 PM PDT 24 |
70618472 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3548928633 |
|
|
Aug 18 05:22:17 PM PDT 24 |
Aug 18 05:22:18 PM PDT 24 |
41923293 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1892250922 |
|
|
Aug 18 05:22:05 PM PDT 24 |
Aug 18 05:22:06 PM PDT 24 |
127667192 ps |
| T62 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3746031756 |
|
|
Aug 18 05:22:38 PM PDT 24 |
Aug 18 05:22:41 PM PDT 24 |
677904770 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3641089823 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:11 PM PDT 24 |
126192489 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.298285288 |
|
|
Aug 18 05:22:36 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
22928877 ps |
| T971 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2782871461 |
|
|
Aug 18 05:22:56 PM PDT 24 |
Aug 18 05:22:57 PM PDT 24 |
121643462 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3572942762 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
13427019 ps |
| T973 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1508067004 |
|
|
Aug 18 05:22:25 PM PDT 24 |
Aug 18 05:22:26 PM PDT 24 |
35018797 ps |
| T974 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3063139844 |
|
|
Aug 18 05:22:28 PM PDT 24 |
Aug 18 05:22:32 PM PDT 24 |
125337339 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.898959179 |
|
|
Aug 18 05:22:36 PM PDT 24 |
Aug 18 05:22:38 PM PDT 24 |
288996694 ps |
| T140 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3845758578 |
|
|
Aug 18 05:21:51 PM PDT 24 |
Aug 18 05:21:53 PM PDT 24 |
203376397 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2273496363 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
34390606 ps |
| T977 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1092219058 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:36 PM PDT 24 |
13046167 ps |
| T90 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.206940777 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:49 PM PDT 24 |
847038484 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1778394200 |
|
|
Aug 18 05:22:45 PM PDT 24 |
Aug 18 05:22:46 PM PDT 24 |
67569171 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.214259605 |
|
|
Aug 18 05:22:20 PM PDT 24 |
Aug 18 05:22:21 PM PDT 24 |
76886371 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.882641439 |
|
|
Aug 18 05:22:26 PM PDT 24 |
Aug 18 05:22:29 PM PDT 24 |
767710045 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.730627521 |
|
|
Aug 18 05:22:07 PM PDT 24 |
Aug 18 05:22:10 PM PDT 24 |
36699209 ps |
| T91 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3787890461 |
|
|
Aug 18 05:22:36 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
23517278 ps |
| T137 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.890995136 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:48 PM PDT 24 |
179465506 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2338808989 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:37 PM PDT 24 |
213866062 ps |
| T982 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.553119563 |
|
|
Aug 18 05:22:45 PM PDT 24 |
Aug 18 05:22:46 PM PDT 24 |
103371984 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1199510579 |
|
|
Aug 18 05:22:08 PM PDT 24 |
Aug 18 05:22:11 PM PDT 24 |
205205717 ps |
| T134 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2251811783 |
|
|
Aug 18 05:22:36 PM PDT 24 |
Aug 18 05:22:39 PM PDT 24 |
998656540 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.723366379 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:11 PM PDT 24 |
453235897 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3730343663 |
|
|
Aug 18 05:22:18 PM PDT 24 |
Aug 18 05:22:20 PM PDT 24 |
132514412 ps |
| T985 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1746344694 |
|
|
Aug 18 05:22:44 PM PDT 24 |
Aug 18 05:22:49 PM PDT 24 |
224399425 ps |
| T139 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.598100176 |
|
|
Aug 18 05:21:59 PM PDT 24 |
Aug 18 05:22:02 PM PDT 24 |
746497351 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.179795154 |
|
|
Aug 18 05:22:27 PM PDT 24 |
Aug 18 05:22:29 PM PDT 24 |
128322434 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2032469996 |
|
|
Aug 18 05:22:00 PM PDT 24 |
Aug 18 05:22:03 PM PDT 24 |
2813882999 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.599247963 |
|
|
Aug 18 05:21:58 PM PDT 24 |
Aug 18 05:22:01 PM PDT 24 |
1647613306 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3810726848 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:36 PM PDT 24 |
44173019 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1201492849 |
|
|
Aug 18 05:22:55 PM PDT 24 |
Aug 18 05:22:59 PM PDT 24 |
862958936 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1111594401 |
|
|
Aug 18 05:22:28 PM PDT 24 |
Aug 18 05:22:29 PM PDT 24 |
61484057 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.748363773 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:51 PM PDT 24 |
149929843 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.29683083 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:10 PM PDT 24 |
94188616 ps |
| T136 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3994748243 |
|
|
Aug 18 05:22:18 PM PDT 24 |
Aug 18 05:22:21 PM PDT 24 |
350163606 ps |
| T141 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3082943007 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:38 PM PDT 24 |
331765216 ps |
| T144 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3380107268 |
|
|
Aug 18 05:22:28 PM PDT 24 |
Aug 18 05:22:30 PM PDT 24 |
1277781521 ps |
| T100 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.788192184 |
|
|
Aug 18 05:22:47 PM PDT 24 |
Aug 18 05:22:51 PM PDT 24 |
1574382001 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4293713509 |
|
|
Aug 18 05:22:45 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
220129840 ps |
| T146 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2256264218 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:47 PM PDT 24 |
186157742 ps |
| T138 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.17594287 |
|
|
Aug 18 05:22:47 PM PDT 24 |
Aug 18 05:22:49 PM PDT 24 |
196007879 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1247449683 |
|
|
Aug 18 05:22:47 PM PDT 24 |
Aug 18 05:22:49 PM PDT 24 |
822383115 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1198067513 |
|
|
Aug 18 05:22:01 PM PDT 24 |
Aug 18 05:22:05 PM PDT 24 |
351211447 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1360211759 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:38 PM PDT 24 |
54484786 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3550399043 |
|
|
Aug 18 05:21:56 PM PDT 24 |
Aug 18 05:22:00 PM PDT 24 |
1591003363 ps |
| T995 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.538120065 |
|
|
Aug 18 05:22:57 PM PDT 24 |
Aug 18 05:22:58 PM PDT 24 |
78510521 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1442514646 |
|
|
Aug 18 05:22:57 PM PDT 24 |
Aug 18 05:22:58 PM PDT 24 |
221167330 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3535256566 |
|
|
Aug 18 05:22:47 PM PDT 24 |
Aug 18 05:22:51 PM PDT 24 |
555647998 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3220357305 |
|
|
Aug 18 05:22:11 PM PDT 24 |
Aug 18 05:22:12 PM PDT 24 |
164386667 ps |
| T999 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1543460112 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:39 PM PDT 24 |
39576418 ps |
| T103 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1651540712 |
|
|
Aug 18 05:22:29 PM PDT 24 |
Aug 18 05:22:32 PM PDT 24 |
482339080 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.307818902 |
|
|
Aug 18 05:22:35 PM PDT 24 |
Aug 18 05:22:40 PM PDT 24 |
424425312 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1895909908 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:48 PM PDT 24 |
142482779 ps |
| T1002 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3800762204 |
|
|
Aug 18 05:22:37 PM PDT 24 |
Aug 18 05:22:38 PM PDT 24 |
42829220 ps |
| T1003 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2465473916 |
|
|
Aug 18 05:22:01 PM PDT 24 |
Aug 18 05:22:02 PM PDT 24 |
62322542 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3634986238 |
|
|
Aug 18 05:22:09 PM PDT 24 |
Aug 18 05:22:10 PM PDT 24 |
60788794 ps |
| T1005 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2696495050 |
|
|
Aug 18 05:22:46 PM PDT 24 |
Aug 18 05:22:46 PM PDT 24 |
36219989 ps |
| T1006 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.454318085 |
|
|
Aug 18 05:22:47 PM PDT 24 |
Aug 18 05:22:49 PM PDT 24 |
33996100 ps |
| T1007 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2576509287 |
|
|
Aug 18 05:22:10 PM PDT 24 |
Aug 18 05:22:12 PM PDT 24 |
461901350 ps |