Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147876218	1			T1	10830		T2	249918		T3	342
instr_valid_dis	116553556	1			T1	10830		T2	97816		T3	342
instr_en	20244308	1			T2	5464		T25	3820		T19	425026

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10620997	1			T25	26566		T19	146152		T7	174934
sram_ifetch_valid_disable	112882982	1			T1	10830		T2	53070		T3	342
sram_ifetch_enable	24372239	1			T2	196848		T25	138116		T19	407682

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147876218	1			T1	10830		T2	249918		T3	342
hw_debug_en_valid_off	113565976	1			T1	10830		T2	131642		T3	342
hw_debug_en_on	22160972	1			T2	118276		T25	96612		T19	471566

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	112882982	1			T1	10830		T2	53070		T3	342
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100614393	1			T1	10830		T2	53070		T3	342
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7912482	1			T19	156730		T7	175218		T45	82
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4526600	1			T19	80028		T7	95800		T45	19122
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1629957	1			T19	40308		T7	12394		T37	35184
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1818770	1			T19	26272		T7	83406		T45	19122
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3545277	1			T25	26566		T19	66124		T7	64992
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1743869	1			T25	26566		T90	96		T145	12754
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1254372	1			T19	20000		T7	64992		T146	83886
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8987186	1			T25	46316		T19	152780		T7	22852
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4077290	1			T25	46316		T19	20360		T45	62570
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3407418	1			T19	68532		T7	22852		T20	36922

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8322250	1			T2	5464		T25	3820		T19	222024
lc_exec_en	9628509	1			T2	118276		T25	23730		T19	252662
valid_exec_dis	109710924	1			T1	10830		T2	97816		T3	342
invalid_exec_dis	34993236	1			T2	196848		T25	164682		T19	553834