Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43608797	1			T1	4945		T2	45341		T3	151
triple_byte_access	2514093	1			T1	100		T2	895		T3	1
halfword_access	3773576	1			T1	150		T2	1313		T3	8
byte_access	5040560	1			T1	171		T2	1847		T3	8
zero_access	1267398	1			T1	49		T2	477		T3	3

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28047361

1

T1

2657

T2

24918

T3

75

auto[1]

28157063

1

T1

2758

T2

24955

T3

96

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21757320	1			T1	2426		T2	22635		T3	66
auto[0]	triple_byte_access	1252563	1			T1	52		T2	457		T4	1122
auto[0]	halfword_access	1882099	1			T1	71		T2	658		T3	4
auto[0]	byte_access	2517504	1			T1	84		T2	921		T3	3
auto[0]	zero_access	637875	1			T1	24		T2	247		T3	2
auto[1]	word_access	21851477	1			T1	2519		T2	22706		T3	85
auto[1]	triple_byte_access	1261530	1			T1	48		T2	438		T3	1
auto[1]	halfword_access	1891477	1			T1	79		T2	655		T3	4
auto[1]	byte_access	2523056	1			T1	87		T2	926		T3	5
auto[1]	zero_access	629523	1			T1	25		T2	230		T3	1