| T797 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1557049778 |
|
|
Aug 19 04:43:42 PM PDT 24 |
Aug 19 04:50:34 PM PDT 24 |
61299267288 ps |
| T798 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1054025654 |
|
|
Aug 19 04:42:15 PM PDT 24 |
Aug 19 04:44:14 PM PDT 24 |
596863217 ps |
| T799 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2615199120 |
|
|
Aug 19 04:44:05 PM PDT 24 |
Aug 19 04:48:31 PM PDT 24 |
755075459 ps |
| T800 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1576514005 |
|
|
Aug 19 04:45:42 PM PDT 24 |
Aug 19 05:25:40 PM PDT 24 |
72698231662 ps |
| T801 |
/workspace/coverage/default/9.sram_ctrl_executable.2446800831 |
|
|
Aug 19 04:42:37 PM PDT 24 |
Aug 19 04:54:42 PM PDT 24 |
7980854192 ps |
| T802 |
/workspace/coverage/default/8.sram_ctrl_executable.3553962429 |
|
|
Aug 19 04:42:42 PM PDT 24 |
Aug 19 04:52:50 PM PDT 24 |
1324765821 ps |
| T803 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.4130454694 |
|
|
Aug 19 04:44:51 PM PDT 24 |
Aug 19 04:49:01 PM PDT 24 |
2614601365 ps |
| T804 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1825584814 |
|
|
Aug 19 04:43:31 PM PDT 24 |
Aug 19 04:45:56 PM PDT 24 |
6182799110 ps |
| T805 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2105514292 |
|
|
Aug 19 04:44:53 PM PDT 24 |
Aug 19 04:46:53 PM PDT 24 |
286136049 ps |
| T806 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3712917472 |
|
|
Aug 19 04:42:59 PM PDT 24 |
Aug 19 04:43:04 PM PDT 24 |
262138308 ps |
| T807 |
/workspace/coverage/default/43.sram_ctrl_executable.2099117418 |
|
|
Aug 19 04:45:37 PM PDT 24 |
Aug 19 04:51:28 PM PDT 24 |
18671743736 ps |
| T808 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1947724489 |
|
|
Aug 19 04:45:36 PM PDT 24 |
Aug 19 04:46:06 PM PDT 24 |
333202756 ps |
| T809 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3183608814 |
|
|
Aug 19 04:44:41 PM PDT 24 |
Aug 19 04:45:39 PM PDT 24 |
7422839646 ps |
| T810 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2296088624 |
|
|
Aug 19 04:43:11 PM PDT 24 |
Aug 19 04:43:17 PM PDT 24 |
638154174 ps |
| T811 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1678528396 |
|
|
Aug 19 04:43:20 PM PDT 24 |
Aug 19 05:10:46 PM PDT 24 |
33897508864 ps |
| T812 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3038025516 |
|
|
Aug 19 04:42:35 PM PDT 24 |
Aug 19 04:45:14 PM PDT 24 |
1522214505 ps |
| T813 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3382869781 |
|
|
Aug 19 04:42:24 PM PDT 24 |
Aug 19 04:42:33 PM PDT 24 |
1770121857 ps |
| T814 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3978091380 |
|
|
Aug 19 04:42:43 PM PDT 24 |
Aug 19 04:42:46 PM PDT 24 |
392372036 ps |
| T815 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3004428047 |
|
|
Aug 19 04:42:13 PM PDT 24 |
Aug 19 04:42:14 PM PDT 24 |
29280103 ps |
| T816 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.387089350 |
|
|
Aug 19 04:45:19 PM PDT 24 |
Aug 19 04:50:02 PM PDT 24 |
34126366421 ps |
| T817 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4190804331 |
|
|
Aug 19 04:46:11 PM PDT 24 |
Aug 19 04:46:20 PM PDT 24 |
533939272 ps |
| T818 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1670178900 |
|
|
Aug 19 04:42:29 PM PDT 24 |
Aug 19 04:47:27 PM PDT 24 |
12440443542 ps |
| T819 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3237156423 |
|
|
Aug 19 04:46:12 PM PDT 24 |
Aug 19 05:02:36 PM PDT 24 |
68008250500 ps |
| T820 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.679256967 |
|
|
Aug 19 04:42:21 PM PDT 24 |
Aug 19 04:42:22 PM PDT 24 |
116715843 ps |
| T821 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2354427884 |
|
|
Aug 19 04:42:10 PM PDT 24 |
Aug 19 04:51:55 PM PDT 24 |
12264894358 ps |
| T822 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1978123353 |
|
|
Aug 19 04:43:19 PM PDT 24 |
Aug 19 04:43:45 PM PDT 24 |
94353267 ps |
| T823 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.557301622 |
|
|
Aug 19 04:45:11 PM PDT 24 |
Aug 19 04:48:21 PM PDT 24 |
5192238499 ps |
| T824 |
/workspace/coverage/default/20.sram_ctrl_regwen.1802708033 |
|
|
Aug 19 04:43:08 PM PDT 24 |
Aug 19 04:57:36 PM PDT 24 |
62004175812 ps |
| T825 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.863328964 |
|
|
Aug 19 04:43:09 PM PDT 24 |
Aug 19 04:43:10 PM PDT 24 |
28893880 ps |
| T826 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2328866241 |
|
|
Aug 19 04:42:11 PM PDT 24 |
Aug 19 04:45:01 PM PDT 24 |
2719175048 ps |
| T827 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1943093113 |
|
|
Aug 19 04:42:51 PM PDT 24 |
Aug 19 04:42:58 PM PDT 24 |
1897766029 ps |
| T828 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.3415872501 |
|
|
Aug 19 04:43:34 PM PDT 24 |
Aug 19 04:43:44 PM PDT 24 |
2804434244 ps |
| T829 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2299784855 |
|
|
Aug 19 04:44:05 PM PDT 24 |
Aug 19 04:44:14 PM PDT 24 |
1290252413 ps |
| T830 |
/workspace/coverage/default/39.sram_ctrl_executable.1967480985 |
|
|
Aug 19 04:44:51 PM PDT 24 |
Aug 19 04:59:31 PM PDT 24 |
14626010263 ps |
| T831 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1288769693 |
|
|
Aug 19 04:42:18 PM PDT 24 |
Aug 19 04:57:25 PM PDT 24 |
10704228707 ps |
| T832 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2510721321 |
|
|
Aug 19 04:42:30 PM PDT 24 |
Aug 19 04:46:16 PM PDT 24 |
9447720267 ps |
| T833 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.581391791 |
|
|
Aug 19 04:42:50 PM PDT 24 |
Aug 19 05:08:00 PM PDT 24 |
3602451299 ps |
| T834 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2882861854 |
|
|
Aug 19 04:42:46 PM PDT 24 |
Aug 19 05:07:02 PM PDT 24 |
24757648230 ps |
| T835 |
/workspace/coverage/default/30.sram_ctrl_stress_all.4180124763 |
|
|
Aug 19 04:44:07 PM PDT 24 |
Aug 19 04:48:25 PM PDT 24 |
1721373856 ps |
| T836 |
/workspace/coverage/default/3.sram_ctrl_executable.3242839575 |
|
|
Aug 19 04:42:17 PM PDT 24 |
Aug 19 04:55:29 PM PDT 24 |
31648017088 ps |
| T837 |
/workspace/coverage/default/35.sram_ctrl_smoke.1620232488 |
|
|
Aug 19 04:44:29 PM PDT 24 |
Aug 19 04:45:55 PM PDT 24 |
130692680 ps |
| T838 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1020641156 |
|
|
Aug 19 04:44:26 PM PDT 24 |
Aug 19 04:44:37 PM PDT 24 |
899074341 ps |
| T839 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.4174247120 |
|
|
Aug 19 04:43:36 PM PDT 24 |
Aug 19 05:01:12 PM PDT 24 |
49854904355 ps |
| T840 |
/workspace/coverage/default/38.sram_ctrl_executable.1198791858 |
|
|
Aug 19 04:44:45 PM PDT 24 |
Aug 19 04:57:37 PM PDT 24 |
16561873554 ps |
| T841 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.320274091 |
|
|
Aug 19 04:42:39 PM PDT 24 |
Aug 19 04:47:46 PM PDT 24 |
6366574632 ps |
| T842 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.3911728964 |
|
|
Aug 19 04:44:05 PM PDT 24 |
Aug 19 04:44:18 PM PDT 24 |
2627743735 ps |
| T843 |
/workspace/coverage/default/16.sram_ctrl_smoke.3062589325 |
|
|
Aug 19 04:43:06 PM PDT 24 |
Aug 19 04:44:26 PM PDT 24 |
121126042 ps |
| T844 |
/workspace/coverage/default/8.sram_ctrl_smoke.4049013472 |
|
|
Aug 19 04:42:38 PM PDT 24 |
Aug 19 04:42:48 PM PDT 24 |
64445135 ps |
| T845 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2269597305 |
|
|
Aug 19 04:46:05 PM PDT 24 |
Aug 19 04:50:15 PM PDT 24 |
2592302301 ps |
| T846 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3025287254 |
|
|
Aug 19 04:46:05 PM PDT 24 |
Aug 19 04:48:09 PM PDT 24 |
825543375 ps |
| T847 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.2631176081 |
|
|
Aug 19 04:42:39 PM PDT 24 |
Aug 19 04:42:49 PM PDT 24 |
779270514 ps |
| T848 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2735132722 |
|
|
Aug 19 04:43:24 PM PDT 24 |
Aug 19 04:43:24 PM PDT 24 |
16139467 ps |
| T849 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.716972907 |
|
|
Aug 19 04:42:18 PM PDT 24 |
Aug 19 04:46:40 PM PDT 24 |
20639667071 ps |
| T850 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1753279350 |
|
|
Aug 19 04:43:03 PM PDT 24 |
Aug 19 05:17:23 PM PDT 24 |
87976619423 ps |
| T851 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1405693312 |
|
|
Aug 19 04:44:30 PM PDT 24 |
Aug 19 04:52:21 PM PDT 24 |
4603204057 ps |
| T852 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3158495603 |
|
|
Aug 19 04:42:50 PM PDT 24 |
Aug 19 04:44:52 PM PDT 24 |
3103618128 ps |
| T853 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3697444102 |
|
|
Aug 19 04:43:27 PM PDT 24 |
Aug 19 04:43:40 PM PDT 24 |
277184259 ps |
| T854 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.885879147 |
|
|
Aug 19 04:46:01 PM PDT 24 |
Aug 19 04:46:02 PM PDT 24 |
50845339 ps |
| T855 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2973128557 |
|
|
Aug 19 04:42:41 PM PDT 24 |
Aug 19 04:44:29 PM PDT 24 |
516520512 ps |
| T856 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.4238293871 |
|
|
Aug 19 04:43:06 PM PDT 24 |
Aug 19 04:43:07 PM PDT 24 |
133337504 ps |
| T857 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2937667729 |
|
|
Aug 19 04:43:26 PM PDT 24 |
Aug 19 06:00:23 PM PDT 24 |
216169671675 ps |
| T858 |
/workspace/coverage/default/44.sram_ctrl_executable.3429421137 |
|
|
Aug 19 04:45:40 PM PDT 24 |
Aug 19 04:58:24 PM PDT 24 |
31879135264 ps |
| T859 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1564668369 |
|
|
Aug 19 04:42:24 PM PDT 24 |
Aug 19 05:37:33 PM PDT 24 |
202944791822 ps |
| T860 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4038082846 |
|
|
Aug 19 04:44:28 PM PDT 24 |
Aug 19 04:44:46 PM PDT 24 |
315438280 ps |
| T861 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1547527925 |
|
|
Aug 19 04:45:12 PM PDT 24 |
Aug 19 04:45:21 PM PDT 24 |
527766899 ps |
| T862 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2447392879 |
|
|
Aug 19 04:43:43 PM PDT 24 |
Aug 19 04:43:49 PM PDT 24 |
274756759 ps |
| T863 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2534393957 |
|
|
Aug 19 04:42:58 PM PDT 24 |
Aug 19 04:43:19 PM PDT 24 |
327458530 ps |
| T864 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2584730641 |
|
|
Aug 19 04:42:39 PM PDT 24 |
Aug 19 04:42:40 PM PDT 24 |
242499502 ps |
| T32 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2906786303 |
|
|
Aug 19 04:42:16 PM PDT 24 |
Aug 19 04:42:19 PM PDT 24 |
618271610 ps |
| T865 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2271542047 |
|
|
Aug 19 04:42:19 PM PDT 24 |
Aug 19 04:42:24 PM PDT 24 |
647328181 ps |
| T866 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1059341695 |
|
|
Aug 19 04:46:06 PM PDT 24 |
Aug 19 04:46:18 PM PDT 24 |
89230409 ps |
| T867 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2806789023 |
|
|
Aug 19 04:43:24 PM PDT 24 |
Aug 19 04:52:04 PM PDT 24 |
89952945269 ps |
| T868 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.938726335 |
|
|
Aug 19 04:46:13 PM PDT 24 |
Aug 19 04:46:14 PM PDT 24 |
27926603 ps |
| T869 |
/workspace/coverage/default/18.sram_ctrl_executable.502393794 |
|
|
Aug 19 04:43:07 PM PDT 24 |
Aug 19 05:03:53 PM PDT 24 |
28932686618 ps |
| T870 |
/workspace/coverage/default/48.sram_ctrl_executable.718138557 |
|
|
Aug 19 04:46:05 PM PDT 24 |
Aug 19 04:52:58 PM PDT 24 |
31132658198 ps |
| T871 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1621683352 |
|
|
Aug 19 04:42:46 PM PDT 24 |
Aug 19 04:43:58 PM PDT 24 |
499638539 ps |
| T872 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1114874154 |
|
|
Aug 19 04:43:51 PM PDT 24 |
Aug 19 04:51:38 PM PDT 24 |
85584914790 ps |
| T873 |
/workspace/coverage/default/24.sram_ctrl_stress_all.4192745562 |
|
|
Aug 19 04:43:38 PM PDT 24 |
Aug 19 05:15:13 PM PDT 24 |
256523516702 ps |
| T874 |
/workspace/coverage/default/35.sram_ctrl_bijection.2633828900 |
|
|
Aug 19 04:44:27 PM PDT 24 |
Aug 19 04:45:48 PM PDT 24 |
27670605191 ps |
| T875 |
/workspace/coverage/default/7.sram_ctrl_executable.920891246 |
|
|
Aug 19 04:42:38 PM PDT 24 |
Aug 19 04:54:56 PM PDT 24 |
68316777541 ps |
| T876 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3151804446 |
|
|
Aug 19 04:43:08 PM PDT 24 |
Aug 19 04:49:32 PM PDT 24 |
18896689968 ps |
| T877 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2823744664 |
|
|
Aug 19 04:42:48 PM PDT 24 |
Aug 19 04:45:16 PM PDT 24 |
537614013 ps |
| T878 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.97746648 |
|
|
Aug 19 04:42:29 PM PDT 24 |
Aug 19 04:43:16 PM PDT 24 |
264932026 ps |
| T879 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.109281104 |
|
|
Aug 19 04:42:36 PM PDT 24 |
Aug 19 04:42:36 PM PDT 24 |
36849580 ps |
| T880 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.926814985 |
|
|
Aug 19 04:44:09 PM PDT 24 |
Aug 19 04:44:12 PM PDT 24 |
342390645 ps |
| T881 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2835856985 |
|
|
Aug 19 04:43:27 PM PDT 24 |
Aug 19 05:00:52 PM PDT 24 |
59435627771 ps |
| T882 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.559126218 |
|
|
Aug 19 04:44:15 PM PDT 24 |
Aug 19 04:56:21 PM PDT 24 |
3460124436 ps |
| T883 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3987300645 |
|
|
Aug 19 04:43:50 PM PDT 24 |
Aug 19 04:46:08 PM PDT 24 |
252522343 ps |
| T884 |
/workspace/coverage/default/23.sram_ctrl_bijection.489858903 |
|
|
Aug 19 04:43:27 PM PDT 24 |
Aug 19 04:44:02 PM PDT 24 |
19520935506 ps |
| T885 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3341635095 |
|
|
Aug 19 04:42:23 PM PDT 24 |
Aug 19 04:42:29 PM PDT 24 |
2020804980 ps |
| T886 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3955299463 |
|
|
Aug 19 04:43:09 PM PDT 24 |
Aug 19 04:43:21 PM PDT 24 |
317110492 ps |
| T887 |
/workspace/coverage/default/22.sram_ctrl_stress_all.2830489857 |
|
|
Aug 19 04:43:25 PM PDT 24 |
Aug 19 06:13:48 PM PDT 24 |
14478102545 ps |
| T122 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2961480899 |
|
|
Aug 19 04:42:20 PM PDT 24 |
Aug 19 04:43:43 PM PDT 24 |
3970557554 ps |
| T888 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3291385912 |
|
|
Aug 19 04:43:10 PM PDT 24 |
Aug 19 04:43:14 PM PDT 24 |
492283972 ps |
| T889 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.752604385 |
|
|
Aug 19 04:44:42 PM PDT 24 |
Aug 19 04:49:06 PM PDT 24 |
9720571882 ps |
| T104 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.644372776 |
|
|
Aug 19 04:43:38 PM PDT 24 |
Aug 19 04:43:42 PM PDT 24 |
183053488 ps |
| T890 |
/workspace/coverage/default/47.sram_ctrl_stress_all.535952029 |
|
|
Aug 19 04:46:05 PM PDT 24 |
Aug 19 04:54:26 PM PDT 24 |
23302723385 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2671371403 |
|
|
Aug 19 04:43:17 PM PDT 24 |
Aug 19 04:43:20 PM PDT 24 |
50076809 ps |
| T892 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3743306358 |
|
|
Aug 19 04:45:39 PM PDT 24 |
Aug 19 04:49:28 PM PDT 24 |
2352582290 ps |
| T893 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3018424520 |
|
|
Aug 19 04:44:06 PM PDT 24 |
Aug 19 04:44:07 PM PDT 24 |
19539308 ps |
| T894 |
/workspace/coverage/default/17.sram_ctrl_executable.3918539991 |
|
|
Aug 19 04:43:03 PM PDT 24 |
Aug 19 04:56:12 PM PDT 24 |
72152380138 ps |
| T895 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2472497373 |
|
|
Aug 19 04:45:52 PM PDT 24 |
Aug 19 04:51:55 PM PDT 24 |
3899641365 ps |
| T896 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3500643086 |
|
|
Aug 19 04:44:10 PM PDT 24 |
Aug 19 04:49:39 PM PDT 24 |
3875870055 ps |
| T897 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.286105554 |
|
|
Aug 19 04:44:09 PM PDT 24 |
Aug 19 04:53:43 PM PDT 24 |
322645977875 ps |
| T898 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1609596893 |
|
|
Aug 19 04:44:53 PM PDT 24 |
Aug 19 04:51:24 PM PDT 24 |
14043133592 ps |
| T899 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1602115067 |
|
|
Aug 19 04:45:03 PM PDT 24 |
Aug 19 04:51:31 PM PDT 24 |
5401048315 ps |
| T900 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.524164641 |
|
|
Aug 19 04:42:59 PM PDT 24 |
Aug 19 04:57:44 PM PDT 24 |
10994276436 ps |
| T901 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.3530321424 |
|
|
Aug 19 04:42:20 PM PDT 24 |
Aug 19 04:42:27 PM PDT 24 |
1315312505 ps |
| T902 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2055819672 |
|
|
Aug 19 04:46:07 PM PDT 24 |
Aug 19 05:07:38 PM PDT 24 |
14585728537 ps |
| T903 |
/workspace/coverage/default/12.sram_ctrl_bijection.1831709456 |
|
|
Aug 19 04:42:48 PM PDT 24 |
Aug 19 04:43:04 PM PDT 24 |
938094621 ps |
| T904 |
/workspace/coverage/default/46.sram_ctrl_executable.2913597554 |
|
|
Aug 19 04:45:50 PM PDT 24 |
Aug 19 04:56:41 PM PDT 24 |
17887925869 ps |
| T905 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.698279070 |
|
|
Aug 19 04:44:53 PM PDT 24 |
Aug 19 04:50:12 PM PDT 24 |
13568052823 ps |
| T906 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1131195288 |
|
|
Aug 19 04:44:16 PM PDT 24 |
Aug 19 04:46:39 PM PDT 24 |
1309164761 ps |
| T907 |
/workspace/coverage/default/41.sram_ctrl_regwen.2741737705 |
|
|
Aug 19 04:45:11 PM PDT 24 |
Aug 19 05:06:55 PM PDT 24 |
28603184439 ps |
| T908 |
/workspace/coverage/default/44.sram_ctrl_partial_access.3245901462 |
|
|
Aug 19 04:45:28 PM PDT 24 |
Aug 19 04:47:05 PM PDT 24 |
818347019 ps |
| T909 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1440199414 |
|
|
Aug 19 04:42:51 PM PDT 24 |
Aug 19 04:42:55 PM PDT 24 |
102733408 ps |
| T910 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.392545364 |
|
|
Aug 19 04:43:44 PM PDT 24 |
Aug 19 04:47:06 PM PDT 24 |
7440494830 ps |
| T911 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1565459269 |
|
|
Aug 19 04:44:29 PM PDT 24 |
Aug 19 04:47:46 PM PDT 24 |
2607335565 ps |
| T912 |
/workspace/coverage/default/29.sram_ctrl_regwen.66521036 |
|
|
Aug 19 04:43:55 PM PDT 24 |
Aug 19 05:04:43 PM PDT 24 |
12518499835 ps |
| T913 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2900410086 |
|
|
Aug 19 04:42:50 PM PDT 24 |
Aug 19 04:45:19 PM PDT 24 |
6150780787 ps |
| T914 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3540474062 |
|
|
Aug 19 04:45:12 PM PDT 24 |
Aug 19 04:59:00 PM PDT 24 |
19833810921 ps |
| T915 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1833207007 |
|
|
Aug 19 04:45:11 PM PDT 24 |
Aug 19 04:56:11 PM PDT 24 |
11755869575 ps |
| T916 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3996488341 |
|
|
Aug 19 04:43:35 PM PDT 24 |
Aug 19 04:43:37 PM PDT 24 |
235743931 ps |
| T917 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3805942653 |
|
|
Aug 19 04:42:46 PM PDT 24 |
Aug 19 06:09:04 PM PDT 24 |
345136961610 ps |
| T918 |
/workspace/coverage/default/16.sram_ctrl_stress_all.4042595330 |
|
|
Aug 19 04:43:01 PM PDT 24 |
Aug 19 05:24:57 PM PDT 24 |
28593338502 ps |
| T919 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2532383942 |
|
|
Aug 19 04:45:55 PM PDT 24 |
Aug 19 04:45:56 PM PDT 24 |
44175232 ps |
| T920 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3823930288 |
|
|
Aug 19 04:42:52 PM PDT 24 |
Aug 19 04:42:53 PM PDT 24 |
66411071 ps |
| T921 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.694179508 |
|
|
Aug 19 04:43:57 PM PDT 24 |
Aug 19 04:44:44 PM PDT 24 |
137239200 ps |
| T922 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1256075619 |
|
|
Aug 19 04:45:02 PM PDT 24 |
Aug 19 04:46:07 PM PDT 24 |
136833748 ps |
| T923 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2052967438 |
|
|
Aug 19 04:43:56 PM PDT 24 |
Aug 19 04:44:03 PM PDT 24 |
61555225 ps |
| T924 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1073322873 |
|
|
Aug 19 04:42:27 PM PDT 24 |
Aug 19 04:43:16 PM PDT 24 |
101747913 ps |
| T925 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2993663154 |
|
|
Aug 19 04:42:48 PM PDT 24 |
Aug 19 04:42:59 PM PDT 24 |
453057843 ps |
| T926 |
/workspace/coverage/default/30.sram_ctrl_regwen.3410512292 |
|
|
Aug 19 04:44:06 PM PDT 24 |
Aug 19 04:49:51 PM PDT 24 |
3444762799 ps |
| T927 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1704019305 |
|
|
Aug 19 04:42:23 PM PDT 24 |
Aug 19 04:42:34 PM PDT 24 |
1565279967 ps |
| T928 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2601834468 |
|
|
Aug 19 04:43:18 PM PDT 24 |
Aug 19 04:43:24 PM PDT 24 |
176455536 ps |
| T929 |
/workspace/coverage/default/13.sram_ctrl_smoke.3988384570 |
|
|
Aug 19 04:42:47 PM PDT 24 |
Aug 19 04:44:35 PM PDT 24 |
146912241 ps |
| T930 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2593039727 |
|
|
Aug 19 04:42:29 PM PDT 24 |
Aug 19 04:48:41 PM PDT 24 |
18770639619 ps |
| T931 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1409032594 |
|
|
Aug 19 04:44:01 PM PDT 24 |
Aug 19 04:44:05 PM PDT 24 |
166601501 ps |
| T932 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1472824400 |
|
|
Aug 19 04:43:19 PM PDT 24 |
Aug 19 04:43:21 PM PDT 24 |
111906845 ps |
| T933 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.3158560323 |
|
|
Aug 19 04:46:03 PM PDT 24 |
Aug 19 04:46:09 PM PDT 24 |
375094148 ps |
| T934 |
/workspace/coverage/default/36.sram_ctrl_partial_access.3785156323 |
|
|
Aug 19 04:44:34 PM PDT 24 |
Aug 19 04:44:45 PM PDT 24 |
1049628475 ps |
| T935 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.3482288560 |
|
|
Aug 19 04:43:50 PM PDT 24 |
Aug 19 04:43:56 PM PDT 24 |
1323555088 ps |
| T936 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2196915274 |
|
|
Aug 19 04:44:06 PM PDT 24 |
Aug 19 04:54:13 PM PDT 24 |
11572854581 ps |
| T937 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2066918656 |
|
|
Aug 19 04:42:29 PM PDT 24 |
Aug 19 04:42:32 PM PDT 24 |
376722810 ps |
| T938 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1398714245 |
|
|
Aug 19 04:26:11 PM PDT 24 |
Aug 19 04:26:15 PM PDT 24 |
127736121 ps |
| T939 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3676390831 |
|
|
Aug 19 04:25:58 PM PDT 24 |
Aug 19 04:25:59 PM PDT 24 |
107049885 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.103988153 |
|
|
Aug 19 04:25:48 PM PDT 24 |
Aug 19 04:25:50 PM PDT 24 |
167932793 ps |
| T941 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2977456320 |
|
|
Aug 19 04:26:13 PM PDT 24 |
Aug 19 04:26:14 PM PDT 24 |
73514220 ps |
| T70 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3798484471 |
|
|
Aug 19 04:26:10 PM PDT 24 |
Aug 19 04:26:11 PM PDT 24 |
39960658 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4122498434 |
|
|
Aug 19 04:25:35 PM PDT 24 |
Aug 19 04:25:36 PM PDT 24 |
17808251 ps |
| T72 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.26104566 |
|
|
Aug 19 04:26:06 PM PDT 24 |
Aug 19 04:26:07 PM PDT 24 |
44448936 ps |
| T80 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1638576029 |
|
|
Aug 19 04:26:13 PM PDT 24 |
Aug 19 04:26:13 PM PDT 24 |
44059409 ps |
| T110 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1255894408 |
|
|
Aug 19 04:25:55 PM PDT 24 |
Aug 19 04:25:56 PM PDT 24 |
34129844 ps |
| T942 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1213936327 |
|
|
Aug 19 04:25:57 PM PDT 24 |
Aug 19 04:25:59 PM PDT 24 |
59375414 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1413018808 |
|
|
Aug 19 04:26:09 PM PDT 24 |
Aug 19 04:26:11 PM PDT 24 |
332390911 ps |
| T68 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1540502956 |
|
|
Aug 19 04:26:19 PM PDT 24 |
Aug 19 04:26:22 PM PDT 24 |
369634382 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3334566643 |
|
|
Aug 19 04:26:02 PM PDT 24 |
Aug 19 04:26:04 PM PDT 24 |
76506769 ps |
| T81 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1699556733 |
|
|
Aug 19 04:26:18 PM PDT 24 |
Aug 19 04:26:20 PM PDT 24 |
224370070 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.634423062 |
|
|
Aug 19 04:26:03 PM PDT 24 |
Aug 19 04:26:04 PM PDT 24 |
68011008 ps |
| T83 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1031936607 |
|
|
Aug 19 04:25:53 PM PDT 24 |
Aug 19 04:25:55 PM PDT 24 |
47325846 ps |
| T115 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2352486598 |
|
|
Aug 19 04:25:38 PM PDT 24 |
Aug 19 04:25:39 PM PDT 24 |
16064268 ps |
| T84 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2471042474 |
|
|
Aug 19 04:25:51 PM PDT 24 |
Aug 19 04:25:54 PM PDT 24 |
1560861739 ps |
| T85 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1127866229 |
|
|
Aug 19 04:25:36 PM PDT 24 |
Aug 19 04:25:37 PM PDT 24 |
44401032 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1340569483 |
|
|
Aug 19 04:26:08 PM PDT 24 |
Aug 19 04:26:08 PM PDT 24 |
72844585 ps |
| T69 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.530664371 |
|
|
Aug 19 04:25:58 PM PDT 24 |
Aug 19 04:26:00 PM PDT 24 |
1302337668 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1340635091 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:59 PM PDT 24 |
1616491104 ps |
| T139 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1980479267 |
|
|
Aug 19 04:26:07 PM PDT 24 |
Aug 19 04:26:09 PM PDT 24 |
593980488 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.82671547 |
|
|
Aug 19 04:26:16 PM PDT 24 |
Aug 19 04:26:18 PM PDT 24 |
422350795 ps |
| T88 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3688457094 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:59 PM PDT 24 |
421263407 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3201937739 |
|
|
Aug 19 04:25:54 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
43284410 ps |
| T132 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3205817451 |
|
|
Aug 19 04:26:00 PM PDT 24 |
Aug 19 04:26:02 PM PDT 24 |
332666559 ps |
| T89 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1490416928 |
|
|
Aug 19 04:25:37 PM PDT 24 |
Aug 19 04:25:38 PM PDT 24 |
34057180 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.943870390 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
17189255 ps |
| T92 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.183306702 |
|
|
Aug 19 04:26:12 PM PDT 24 |
Aug 19 04:26:15 PM PDT 24 |
540877199 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.872197835 |
|
|
Aug 19 04:25:49 PM PDT 24 |
Aug 19 04:25:50 PM PDT 24 |
28749344 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2633460604 |
|
|
Aug 19 04:26:00 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
41156908 ps |
| T948 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.350565900 |
|
|
Aug 19 04:26:15 PM PDT 24 |
Aug 19 04:26:17 PM PDT 24 |
37226821 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3093838839 |
|
|
Aug 19 04:26:04 PM PDT 24 |
Aug 19 04:26:05 PM PDT 24 |
59896449 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3222373840 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
14238913 ps |
| T133 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.321565396 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
158704683 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2897893824 |
|
|
Aug 19 04:26:09 PM PDT 24 |
Aug 19 04:26:12 PM PDT 24 |
60873015 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1563877026 |
|
|
Aug 19 04:26:12 PM PDT 24 |
Aug 19 04:26:12 PM PDT 24 |
104796119 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4087859324 |
|
|
Aug 19 04:25:54 PM PDT 24 |
Aug 19 04:25:54 PM PDT 24 |
21015755 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1144617102 |
|
|
Aug 19 04:25:58 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
112131709 ps |
| T955 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4147472279 |
|
|
Aug 19 04:26:09 PM PDT 24 |
Aug 19 04:26:11 PM PDT 24 |
123822297 ps |
| T956 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.803740108 |
|
|
Aug 19 04:26:10 PM PDT 24 |
Aug 19 04:26:11 PM PDT 24 |
13822325 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3524235170 |
|
|
Aug 19 04:26:00 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
98325469 ps |
| T958 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.955879242 |
|
|
Aug 19 04:26:11 PM PDT 24 |
Aug 19 04:26:12 PM PDT 24 |
53071871 ps |
| T959 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2609786446 |
|
|
Aug 19 04:25:55 PM PDT 24 |
Aug 19 04:25:56 PM PDT 24 |
60263868 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.127198141 |
|
|
Aug 19 04:25:58 PM PDT 24 |
Aug 19 04:26:00 PM PDT 24 |
129775878 ps |
| T140 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1049897747 |
|
|
Aug 19 04:25:53 PM PDT 24 |
Aug 19 04:25:55 PM PDT 24 |
106229075 ps |
| T137 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.827956182 |
|
|
Aug 19 04:25:42 PM PDT 24 |
Aug 19 04:25:44 PM PDT 24 |
259478417 ps |
| T93 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.382511839 |
|
|
Aug 19 04:25:57 PM PDT 24 |
Aug 19 04:25:58 PM PDT 24 |
40482301 ps |
| T961 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1589374020 |
|
|
Aug 19 04:26:10 PM PDT 24 |
Aug 19 04:26:11 PM PDT 24 |
16211211 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.684826667 |
|
|
Aug 19 04:25:42 PM PDT 24 |
Aug 19 04:25:46 PM PDT 24 |
69760948 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1006308964 |
|
|
Aug 19 04:26:00 PM PDT 24 |
Aug 19 04:26:00 PM PDT 24 |
26835577 ps |
| T143 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1137550015 |
|
|
Aug 19 04:26:14 PM PDT 24 |
Aug 19 04:26:17 PM PDT 24 |
194980621 ps |
| T964 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3943885235 |
|
|
Aug 19 04:26:01 PM PDT 24 |
Aug 19 04:26:03 PM PDT 24 |
37265762 ps |
| T134 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1823569550 |
|
|
Aug 19 04:25:59 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
843368604 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1672965206 |
|
|
Aug 19 04:26:09 PM PDT 24 |
Aug 19 04:26:10 PM PDT 24 |
15712960 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1689464333 |
|
|
Aug 19 04:25:55 PM PDT 24 |
Aug 19 04:25:58 PM PDT 24 |
54934836 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1971143537 |
|
|
Aug 19 04:26:11 PM PDT 24 |
Aug 19 04:26:12 PM PDT 24 |
47942193 ps |
| T138 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2297107470 |
|
|
Aug 19 04:26:10 PM PDT 24 |
Aug 19 04:26:12 PM PDT 24 |
284141822 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.885430 |
|
|
Aug 19 04:26:12 PM PDT 24 |
Aug 19 04:26:13 PM PDT 24 |
24990839 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.106859001 |
|
|
Aug 19 04:26:10 PM PDT 24 |
Aug 19 04:26:13 PM PDT 24 |
2334915418 ps |
| T94 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3438319067 |
|
|
Aug 19 04:25:55 PM PDT 24 |
Aug 19 04:25:59 PM PDT 24 |
3070191261 ps |
| T95 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.209304761 |
|
|
Aug 19 04:26:02 PM PDT 24 |
Aug 19 04:26:03 PM PDT 24 |
89604632 ps |
| T141 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3774129238 |
|
|
Aug 19 04:25:55 PM PDT 24 |
Aug 19 04:25:58 PM PDT 24 |
249859257 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.745717725 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
72129125 ps |
| T970 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2522077905 |
|
|
Aug 19 04:25:59 PM PDT 24 |
Aug 19 04:26:04 PM PDT 24 |
290623065 ps |
| T108 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.385101288 |
|
|
Aug 19 04:25:57 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
46939437 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2025636567 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:58 PM PDT 24 |
156874387 ps |
| T109 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4088131144 |
|
|
Aug 19 04:26:00 PM PDT 24 |
Aug 19 04:26:02 PM PDT 24 |
246098730 ps |
| T972 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.554540230 |
|
|
Aug 19 04:25:57 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
464247839 ps |
| T142 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1152862088 |
|
|
Aug 19 04:25:55 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
331721568 ps |
| T973 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.145756935 |
|
|
Aug 19 04:26:04 PM PDT 24 |
Aug 19 04:26:05 PM PDT 24 |
80910173 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3212795983 |
|
|
Aug 19 04:25:58 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
421302395 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.385641057 |
|
|
Aug 19 04:25:55 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
242447323 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2945115373 |
|
|
Aug 19 04:25:37 PM PDT 24 |
Aug 19 04:25:40 PM PDT 24 |
513205543 ps |
| T977 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.946418155 |
|
|
Aug 19 04:25:59 PM PDT 24 |
Aug 19 04:26:00 PM PDT 24 |
16674023 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2831250021 |
|
|
Aug 19 04:25:58 PM PDT 24 |
Aug 19 04:25:59 PM PDT 24 |
34731539 ps |
| T979 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4052746989 |
|
|
Aug 19 04:25:59 PM PDT 24 |
Aug 19 04:26:00 PM PDT 24 |
24292553 ps |
| T96 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1715065557 |
|
|
Aug 19 04:26:14 PM PDT 24 |
Aug 19 04:26:15 PM PDT 24 |
21546708 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.134350996 |
|
|
Aug 19 04:25:59 PM PDT 24 |
Aug 19 04:26:00 PM PDT 24 |
21806434 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2279832457 |
|
|
Aug 19 04:26:00 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
54100990 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1124933010 |
|
|
Aug 19 04:26:06 PM PDT 24 |
Aug 19 04:26:10 PM PDT 24 |
136067671 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3041104052 |
|
|
Aug 19 04:26:01 PM PDT 24 |
Aug 19 04:26:05 PM PDT 24 |
1696539670 ps |
| T97 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3569615336 |
|
|
Aug 19 04:25:57 PM PDT 24 |
Aug 19 04:25:58 PM PDT 24 |
14864721 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2253704037 |
|
|
Aug 19 04:25:58 PM PDT 24 |
Aug 19 04:25:58 PM PDT 24 |
70784424 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1160774310 |
|
|
Aug 19 04:25:54 PM PDT 24 |
Aug 19 04:25:55 PM PDT 24 |
12030239 ps |
| T985 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3190301801 |
|
|
Aug 19 04:26:10 PM PDT 24 |
Aug 19 04:26:10 PM PDT 24 |
23987579 ps |
| T107 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2390818282 |
|
|
Aug 19 04:26:02 PM PDT 24 |
Aug 19 04:26:04 PM PDT 24 |
414198997 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3852580061 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
186345471 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2729695542 |
|
|
Aug 19 04:25:54 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
446178554 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3565244478 |
|
|
Aug 19 04:26:02 PM PDT 24 |
Aug 19 04:26:03 PM PDT 24 |
69266668 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.111980505 |
|
|
Aug 19 04:26:01 PM PDT 24 |
Aug 19 04:26:01 PM PDT 24 |
23519001 ps |
| T990 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2556569477 |
|
|
Aug 19 04:26:09 PM PDT 24 |
Aug 19 04:26:13 PM PDT 24 |
40117053 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4288600579 |
|
|
Aug 19 04:26:01 PM PDT 24 |
Aug 19 04:26:03 PM PDT 24 |
46598644 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1646835422 |
|
|
Aug 19 04:26:01 PM PDT 24 |
Aug 19 04:26:04 PM PDT 24 |
1571940786 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4244503704 |
|
|
Aug 19 04:25:42 PM PDT 24 |
Aug 19 04:25:43 PM PDT 24 |
181969582 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2279157663 |
|
|
Aug 19 04:26:05 PM PDT 24 |
Aug 19 04:26:07 PM PDT 24 |
204269747 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3996550317 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:57 PM PDT 24 |
17618715 ps |
| T996 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.46984359 |
|
|
Aug 19 04:26:00 PM PDT 24 |
Aug 19 04:26:02 PM PDT 24 |
647899460 ps |
| T135 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.912551693 |
|
|
Aug 19 04:25:57 PM PDT 24 |
Aug 19 04:26:00 PM PDT 24 |
176331907 ps |
| T144 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1236846218 |
|
|
Aug 19 04:25:56 PM PDT 24 |
Aug 19 04:25:58 PM PDT 24 |
411849651 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.15228528 |
|
|
Aug 19 04:25:52 PM PDT 24 |
Aug 19 04:25:54 PM PDT 24 |
174656336 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.972426949 |
|
|
Aug 19 04:26:12 PM PDT 24 |
Aug 19 04:26:16 PM PDT 24 |
28738810 ps |
| T136 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.84175497 |
|
|
Aug 19 04:26:05 PM PDT 24 |
Aug 19 04:26:08 PM PDT 24 |
556591661 ps |
| T999 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2554685777 |
|
|
Aug 19 04:26:01 PM PDT 24 |
Aug 19 04:26:05 PM PDT 24 |
72276685 ps |
| T1000 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4252360983 |
|
|
Aug 19 04:26:13 PM PDT 24 |
Aug 19 04:26:16 PM PDT 24 |
46433127 ps |