Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 42664 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 31224 1 T4 1 T1 18 T5 7



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 44013 1 T4 1 T1 21 T5 22
values_0 14538 1 T1 9 T2 6 T3 8
values_1 15337 1 T1 13 T2 16 T3 14



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 29671 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 44217 1 T4 1 T1 25 T5 9



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 411 1 T60 1 T61 1 T13 8
valid_sources_01 354 1 T62 1 T14 2 T16 10
valid_sources_02 276 1 T63 1 T64 1 T65 1
valid_sources_03 410 1 T3 1 T25 3 T66 1
valid_sources_04 269 1 T27 21 T14 1 T16 13
valid_sources_05 318 1 T2 1 T67 1 T68 2
valid_sources_06 339 1 T2 1 T28 1 T69 2
valid_sources_07 166 1 T1 1 T69 1 T65 1
valid_sources_08 374 1 T70 2 T71 1 T14 6
valid_sources_09 297 1 T3 1 T25 1 T61 1
valid_sources_0a 318 1 T26 2 T69 1 T72 43
valid_sources_0b 236 1 T26 1 T73 1 T14 1
valid_sources_0c 334 1 T25 3 T74 45 T31 2
valid_sources_0d 293 1 T75 1 T76 1 T71 1
valid_sources_0e 269 1 T67 1 T77 1 T78 1
valid_sources_0f 296 1 T79 1 T67 2 T80 1
valid_sources_10 244 1 T25 3 T64 2 T65 1
valid_sources_11 262 1 T81 2 T82 6 T83 1
valid_sources_12 203 1 T26 2 T48 1 T84 5
valid_sources_13 467 1 T62 1 T65 1 T14 2
valid_sources_14 350 1 T25 1 T67 2 T69 1
valid_sources_15 323 1 T64 1 T85 2 T14 1
valid_sources_16 252 1 T86 1 T79 1 T87 1
valid_sources_17 296 1 T62 1 T65 1 T88 1
valid_sources_18 204 1 T1 5 T75 6 T89 1
valid_sources_19 272 1 T66 1 T90 1 T80 1
valid_sources_1a 310 1 T75 3 T60 1 T91 1
valid_sources_1b 291 1 T25 1 T75 1 T68 4
valid_sources_1c 164 1 T26 1 T92 1 T66 1
valid_sources_1d 323 1 T48 2 T63 1 T93 1
valid_sources_1e 325 1 T28 1 T83 1 T70 1
valid_sources_1f 375 1 T25 1 T94 3 T28 1
valid_sources_20 273 1 T26 1 T95 1 T96 3
valid_sources_21 158 1 T2 1 T3 1 T79 1
valid_sources_22 216 1 T69 1 T89 1 T93 1
valid_sources_23 383 1 T1 1 T12 49 T31 2
valid_sources_24 502 1 T97 1 T69 1 T76 1
valid_sources_25 347 1 T29 5 T66 2 T62 1
valid_sources_26 354 1 T3 2 T86 1 T96 1
valid_sources_27 402 1 T3 1 T75 1 T68 2
valid_sources_28 169 1 T26 1 T69 1 T85 1
valid_sources_29 280 1 T98 2 T31 2 T99 1
valid_sources_2a 239 1 T2 6 T31 1 T70 1
valid_sources_2b 165 1 T25 1 T31 3 T79 1
valid_sources_2c 332 1 T3 1 T25 1 T28 1
valid_sources_2d 331 1 T2 1 T66 1 T79 1
valid_sources_2e 210 1 T6 2 T67 2 T68 4
valid_sources_2f 340 1 T31 2 T66 2 T76 2
valid_sources_30 232 1 T68 1 T80 2 T78 1
valid_sources_31 310 1 T97 2 T29 5 T88 2
valid_sources_32 328 1 T3 1 T75 1 T67 1
valid_sources_33 322 1 T28 1 T79 1 T69 1
valid_sources_34 262 1 T66 1 T100 1 T101 1
valid_sources_35 389 1 T3 2 T28 1 T62 1
valid_sources_36 216 1 T26 2 T60 1 T80 1
valid_sources_37 403 1 T28 1 T89 1 T102 2
valid_sources_38 310 1 T65 2 T89 1 T82 3
valid_sources_39 243 1 T2 1 T66 1 T60 1
valid_sources_3a 172 1 T26 1 T28 1 T79 1
valid_sources_3b 204 1 T31 1 T62 1 T79 1
valid_sources_3c 282 1 T31 3 T46 39 T89 1
valid_sources_3d 335 1 T1 2 T103 43 T93 1
valid_sources_3e 298 1 T69 2 T77 3 T104 43
valid_sources_3f 301 1 T105 1 T93 1 T70 1
valid_sources_40 217 1 T106 11 T70 1 T14 3
valid_sources_41 249 1 T62 1 T79 2 T69 2
valid_sources_42 307 1 T62 1 T63 1 T75 1
valid_sources_43 202 1 T107 4 T97 2 T28 1
valid_sources_44 273 1 T25 1 T26 3 T28 1
valid_sources_45 271 1 T108 46 T65 1 T80 1
valid_sources_46 265 1 T98 2 T79 1 T77 1
valid_sources_47 463 1 T31 1 T109 1 T68 2
valid_sources_48 346 1 T62 1 T65 1 T60 1
valid_sources_49 255 1 T79 2 T60 1 T93 2
valid_sources_4a 315 1 T26 1 T28 1 T63 1
valid_sources_4b 431 1 T26 1 T62 1 T67 1
valid_sources_4c 177 1 T62 1 T64 3 T110 1
valid_sources_4d 260 1 T2 1 T94 3 T111 1
valid_sources_4e 234 1 T29 1 T88 1 T101 1
valid_sources_4f 259 1 T64 3 T105 1 T13 9
valid_sources_50 221 1 T3 2 T28 1 T66 1
valid_sources_51 133 1 T3 2 T31 1 T85 1
valid_sources_52 317 1 T48 2 T80 1 T100 1
valid_sources_53 481 1 T31 1 T48 3 T60 1
valid_sources_54 192 1 T66 1 T75 2 T93 1
valid_sources_55 169 1 T3 1 T79 1 T75 1
valid_sources_56 210 1 T25 1 T101 2 T76 1
valid_sources_57 266 1 T98 1 T95 1 T48 1
valid_sources_58 232 1 T31 1 T68 1 T60 1
valid_sources_59 242 1 T28 2 T79 1 T70 1
valid_sources_5a 236 1 T48 1 T65 1 T89 2
valid_sources_5b 228 1 T29 6 T66 1 T75 2
valid_sources_5c 363 1 T29 3 T66 2 T112 1
valid_sources_5d 237 1 T69 1 T60 1 T113 43
valid_sources_5e 318 1 T48 3 T79 1 T75 1
valid_sources_5f 424 1 T28 1 T79 2 T68 1
valid_sources_60 300 1 T2 4 T79 1 T77 1
valid_sources_61 257 1 T1 1 T8 11 T48 1
valid_sources_62 221 1 T66 1 T75 1 T64 3
valid_sources_63 343 1 T1 11 T94 1 T86 1
valid_sources_64 339 1 T2 1 T81 1 T71 1
valid_sources_65 287 1 T29 6 T66 1 T67 3
valid_sources_66 227 1 T2 1 T26 1 T28 1
valid_sources_67 322 1 T3 1 T31 1 T77 1
valid_sources_68 195 1 T28 1 T66 1 T62 3
valid_sources_69 317 1 T6 3 T60 1 T114 1
valid_sources_6a 276 1 T2 1 T69 1 T60 1
valid_sources_6b 341 1 T67 1 T65 1 T115 37
valid_sources_6c 207 1 T26 1 T28 1 T89 1
valid_sources_6d 220 1 T86 1 T69 1 T81 1
valid_sources_6e 250 1 T2 1 T28 1 T66 1
valid_sources_6f 274 1 T69 1 T70 1 T14 5
valid_sources_70 290 1 T116 1 T14 2 T33 1
valid_sources_71 294 1 T27 22 T28 1 T31 1
valid_sources_72 232 1 T48 3 T83 1 T100 1
valid_sources_73 196 1 T4 1 T62 1 T67 1
valid_sources_74 226 1 T3 1 T69 1 T70 1
valid_sources_75 258 1 T31 2 T65 1 T84 2
valid_sources_76 222 1 T25 3 T26 1 T98 2
valid_sources_77 222 1 T66 1 T64 1 T117 1
valid_sources_78 270 1 T107 1 T67 1 T69 1
valid_sources_79 181 1 T3 1 T62 1 T79 1
valid_sources_7a 206 1 T3 2 T28 1 T84 2
valid_sources_7b 302 1 T3 1 T26 1 T67 1
valid_sources_7c 246 1 T80 1 T89 1 T100 1
valid_sources_7d 240 1 T26 1 T75 2 T77 2
valid_sources_7e 353 1 T1 9 T65 1 T84 1
valid_sources_7f 335 1 T2 2 T28 1 T75 1
valid_sources_80 244 1 T62 1 T79 1 T69 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 17254 1 T4 1 T1 12 T5 7
values_0 all_enables biggest_size 8326 1 T1 2 T2 2 T3 4
values_1 all_enables biggest_size 5644 1 T1 4 T2 3 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%