Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 93.16 99.57 82.92 98.98 92.78 91.55
dut 93.16 99.57 82.92 98.98 92.78 91.55
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 73.98 100.00 100.00 95.92 0.00
tlul_assert_device 99.07 100.00 100.00 97.20
u_prim_flop_2sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_intr_hw 100.00 100.00 100.00
u_reg 93.93 99.57 95.70 96.67 83.78
subtree...
u_sysrst_ctrl_autoblock 81.22 100.00 72.22 71.43
u_sysrst_ctrl_detect 86.87 100.00 83.33 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
u_sysrst_ctrl_combo 80.85 100.00 68.75 73.81
gen_combo_trigger[0].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[0].u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce 86.87 100.00 83.33 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_combo_trigger[1].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[1].u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce 86.87 100.00 83.33 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_combo_trigger[2].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[2].u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce 86.87 100.00 83.33 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_combo_trigger[3].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[3].u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce 86.87 100.00 83.33 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
u_sysrst_ctrl_keyintr 84.73 100.00 76.92 77.27
gen_keyfsm[0].u_sysrst_ctrl_detect 84.73 100.00 76.92 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_keyfsm[1].u_sysrst_ctrl_detect 84.73 100.00 76.92 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_keyfsm[2].u_sysrst_ctrl_detect 84.73 100.00 76.92 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_keyfsm[3].u_sysrst_ctrl_detect 84.73 100.00 76.92 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_keyfsm[4].u_sysrst_ctrl_detect 84.73 100.00 76.92 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
gen_keyfsm[5].u_sysrst_ctrl_detect 84.73 100.00 76.92 77.27
u_prim_filter_ctr 85.00 100.00 80.00 75.00
u_sysrst_ctrl_pin 56.94 100.00 20.83 50.00
u_cfg_ac_present_i_pin 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_ulp 81.81 96.30 75.00 74.14
u_sysrst_ctrl_detect_ac_present 81.02 95.83 75.00 72.22
u_prim_filter_ctr 82.62 92.86 80.00 75.00
u_sysrst_ctrl_detect_lid_open 82.10 96.30 75.00 75.00
u_prim_filter_ctr 82.62 92.86 80.00 75.00
u_sysrst_ctrl_detect_pwrb 82.10 96.30 75.00 75.00
u_prim_filter_ctr 82.62 92.86 80.00 75.00
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