Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_detect
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.80 100.00 62.50 73.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present 77.78 100.00 66.67 66.67
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb 80.56 100.00 66.67 75.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open 80.56 100.00 66.67 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect 85.00 100.00 75.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect 85.00 100.00 75.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect 85.00 100.00 75.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect 85.00 100.00 75.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect 85.00 100.00 75.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect 85.00 100.00 75.00 80.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect 88.57 100.00 85.71 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce 88.57 100.00 85.71 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce 88.57 100.00 85.71 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce 88.57 100.00 85.71 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce 88.57 100.00 85.71 80.00



Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 100.00 66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.02 95.83 75.00 72.22


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 82.62 92.86 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.56 100.00 66.67 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.10 96.30 75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 82.62 92.86 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.56 100.00 66.67 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.10 96.30 75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 82.62 92.86 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 100.00 75.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.73 100.00 76.92 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 100.00 75.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.73 100.00 76.92 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 100.00 75.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.73 100.00 76.92 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 100.00 75.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.73 100.00 76.92 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 100.00 75.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.73 100.00 76.92 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 100.00 75.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.73 100.00 76.92 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.57 100.00 85.71 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.87 100.00 83.33 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 100.00 50.00 50.00 u_sysrst_ctrl_autoblock


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.57 100.00 85.71 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.87 100.00 83.33 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.57 100.00 85.71 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.87 100.00 83.33 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.57 100.00 85.71 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.87 100.00 83.33 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.57 100.00 85.71 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.87 100.00 83.33 77.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_filter_ctr 85.00 100.00 80.00 75.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=0 + TimerWidth=32,EdgeDetect=1,Sticky=0 )
Line Coverage for Module self-instances :
SCORELINE
88.57 100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORELINE
85.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect

SCORELINE
85.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

SCORELINE
85.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect

SCORELINE
85.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect

SCORELINE
85.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

SCORELINE
85.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect

SCORELINE
88.57 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce

SCORELINE
88.57 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce

SCORELINE
88.57 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce

SCORELINE
88.57 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce

SCORELINE
80.56 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORELINE
80.56 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Line Coverage for Module : sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=0,Sticky=1 )
Line Coverage for Module self-instances :
SCORELINE
77.78 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6600
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8800
CONT_ASSIGN8911100.00
CONT_ASSIGN9000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
57 1 1
58 1 1
65 1 1
66 unreachable
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 unreachable
89 1 1
90 unreachable


Cond Coverage for Module : sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=0 + TimerWidth=32,EdgeDetect=1,Sticky=0 )
Cond Coverage for Module self-instances :
SCORECOND
88.57 85.71
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORECOND
85.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect

SCORECOND
85.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

SCORECOND
85.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect

SCORECOND
85.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect

SCORECOND
85.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

SCORECOND
85.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect

SCORECOND
88.57 85.71
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce

SCORECOND
88.57 85.71
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce

SCORECOND
88.57 85.71
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce

SCORECOND
88.57 85.71
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce

TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Cond Coverage for Module : sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=1 + TimerWidth=16,EdgeDetect=0,Sticky=1 )
Cond Coverage for Module self-instances :
SCORECOND
80.56 66.67
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORECOND
80.56 66.67
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORECOND
77.78 66.67
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       65
 EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       66
 EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Module : sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=0 + TimerWidth=32,EdgeDetect=1,Sticky=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
88.57 80.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCOREBRANCH
85.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect

SCOREBRANCH
85.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

SCOREBRANCH
85.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect

SCOREBRANCH
85.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect

SCOREBRANCH
85.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

SCOREBRANCH
85.00 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect

SCOREBRANCH
88.57 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce

SCOREBRANCH
88.57 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce

SCOREBRANCH
88.57 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce

SCOREBRANCH
88.57 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce

Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Branch Coverage for Module : sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=0,Sticky=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
77.78 66.67
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Line No.TotalCoveredPercent
Branches 6 4 66.67
TERNARY 65 2 1 50.00
TERNARY 66 2 1 50.00
IF 78 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 65 (cfg_l2h_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 66 (cfg_h2l_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Branch Coverage for Module : sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
80.56 75.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCOREBRANCH
80.56 75.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Line No.TotalCoveredPercent
Branches 8 6 75.00
TERNARY 65 2 1 50.00
TERNARY 66 2 1 50.00
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 65 (cfg_l2h_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 66 (cfg_h2l_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6600
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8800
CONT_ASSIGN8911100.00
CONT_ASSIGN9000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
57 1 1
58 1 1
65 1 1
66 unreachable
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 unreachable
89 1 1
90 unreachable


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       66
 EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
Branches 6 4 66.67
TERNARY 65 2 1 50.00
TERNARY 66 2 1 50.00
IF 78 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 65 (cfg_l2h_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 66 (cfg_h2l_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
TOTAL1313100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6900
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8700
CONT_ASSIGN8811100.00
CONT_ASSIGN8900
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 unreachable
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 unreachable
88 1 1
89 unreachable
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

 LINE       66
 EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
Branches 8 6 75.00
TERNARY 65 2 1 50.00
TERNARY 66 2 1 50.00
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 65 (cfg_l2h_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 66 (cfg_h2l_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
TOTAL1313100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7200
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8800
CONT_ASSIGN8911100.00
CONT_ASSIGN9000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 unreachable
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 unreachable
89 1 1
90 unreachable


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       66
 EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
             ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
Branches 8 6 75.00
TERNARY 65 2 1 50.00
TERNARY 66 2 1 50.00
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 65 (cfg_l2h_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 66 (cfg_h2l_en_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions7685.71
Logical7685.71
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce
TotalCoveredPercent
Conditions7685.71
Logical7685.71
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce
TotalCoveredPercent
Conditions7685.71
Logical7685.71
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce
TotalCoveredPercent
Conditions7685.71
Logical7685.71
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7211100.00
ALWAYS7855100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
49 1 1
50 1 1
52 1 1
69 1 1
72 1 1
78 1 1
79 1 1
80 1 1
82 1 1
83 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce
TotalCoveredPercent
Conditions7685.71
Logical7685.71
Non-Logical00
Event00

 LINE       69
 EXPRESSION (((~trigger_debounced_d)) ? 1'b0 : (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0))
             ------------1-----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       69
 SUB-EXPRESSION (cfg_l2h_en_i ? ((l2h_event | l2h_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 EXPRESSION (trigger_debounced_d ? 1'b0 : (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0))
             ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       72
 SUB-EXPRESSION (cfg_h2l_en_i ? ((h2l_event | h2l_detected_q)) : 1'b0)
                 ------1-----
-1-StatusTests
0CoveredT4,T1,T5
1Unreachable

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce
Line No.TotalCoveredPercent
Branches 10 8 80.00
TERNARY 69 3 2 66.67
TERNARY 72 3 2 66.67
IF 78 2 2 100.00
IF 49 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 ((~trigger_debounced_d)) ? -2-: 69 (cfg_l2h_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (trigger_debounced_d) ? -2-: 72 (cfg_h2l_en_i) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 78 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%