Module Definition
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Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 100.00 53.33 62.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : sysrst_ctrl_comboact
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS801111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
71 1 1
72 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
90 1 1
91 1 1


Cond Coverage for Module : sysrst_ctrl_comboact
TotalCoveredPercent
Conditions15853.33
Logical15853.33
Non-Logical00
Event00

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse)
                 ---------1--------    -------2-------    ---------3--------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT4,T1,T5
010Not Covered
100Not Covered

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       71
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11Not Covered

 LINE       72
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T1,T5

Branch Coverage for Module : sysrst_ctrl_comboact
Line No.TotalCoveredPercent
Branches 8 5 62.50
TERNARY 63 3 2 66.67
TERNARY 72 3 1 33.33
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 (((combo_ec_rst_pulse || combo_gsc_pulse) || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (timer_expired) ? -2-: 72 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T1,T5
0 0 Not Covered


LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS801111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
71 1 1
72 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
90 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
TotalCoveredPercent
Conditions15853.33
Logical15853.33
Non-Logical00
Event00

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse)
                 ---------1--------    -------2-------    ---------3--------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT4,T1,T5
010Not Covered
100Not Covered

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       71
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11Not Covered

 LINE       72
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
Line No.TotalCoveredPercent
Branches 8 5 62.50
TERNARY 63 3 2 66.67
TERNARY 72 3 1 33.33
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 (((combo_ec_rst_pulse || combo_gsc_pulse) || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (timer_expired) ? -2-: 72 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T1,T5
0 0 Not Covered


LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS801111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
71 1 1
72 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
90 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
TotalCoveredPercent
Conditions15853.33
Logical15853.33
Non-Logical00
Event00

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse)
                 ---------1--------    -------2-------    ---------3--------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT4,T1,T5
010Not Covered
100Not Covered

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       71
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11Not Covered

 LINE       72
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
Line No.TotalCoveredPercent
Branches 8 5 62.50
TERNARY 63 3 2 66.67
TERNARY 72 3 1 33.33
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 (((combo_ec_rst_pulse || combo_gsc_pulse) || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (timer_expired) ? -2-: 72 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T1,T5
0 0 Not Covered


LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS801111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
71 1 1
72 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
90 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
TotalCoveredPercent
Conditions15853.33
Logical15853.33
Non-Logical00
Event00

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse)
                 ---------1--------    -------2-------    ---------3--------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT4,T1,T5
010Not Covered
100Not Covered

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       71
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11Not Covered

 LINE       72
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
Line No.TotalCoveredPercent
Branches 8 5 62.50
TERNARY 63 3 2 66.67
TERNARY 72 3 1 33.33
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 (((combo_ec_rst_pulse || combo_gsc_pulse) || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (timer_expired) ? -2-: 72 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T1,T5
0 0 Not Covered


LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS801111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
71 1 1
72 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
85 1 1
87 1 1
88 1 1
89 1 1
90 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
TotalCoveredPercent
Conditions15853.33
Logical15853.33
Non-Logical00
Event00

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || combo_gsc_pulse || ec_rst_l_det_pulse)
                 ---------1--------    -------2-------    ---------3--------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT4,T1,T5
010Not Covered
100Not Covered

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       71
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11Not Covered

 LINE       72
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1Not Covered

 LINE       72
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
Line No.TotalCoveredPercent
Branches 8 5 62.50
TERNARY 63 3 2 66.67
TERNARY 72 3 1 33.33
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 (((combo_ec_rst_pulse || combo_gsc_pulse) || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Not Covered
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 72 (timer_expired) ? -2-: 72 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T1,T5
0 0 Not Covered


LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%