Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.98 100.00 100.00 95.92 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 73.98 100.00 100.00 95.92 0.00



Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.98 100.00 100.00 95.92 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.98 100.00 100.00 95.92 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.98 100.00 25.00 98.93 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_csr_assert_fpv
Line No.TotalCoveredPercent
TOTAL8080100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS533030100.00
CONT_ASSIGN9811100.00
ALWAYS1024545100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv' or '../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
45 1 1
46 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
77 1 1
78 1 1
79 1 1
80 1 1
81 1 1
82 1 1
98 1 1
102 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
111 1 1
112 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
==> MISSING_ELSE
MISSING_ELSE
143 1 1
144 1 1
145 1 1
146 1 1
==> MISSING_ELSE
148 1 1
MISSING_ELSE
150 1 1
151 1 1
MISSING_ELSE
MISSING_ELSE


Cond Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalCoveredPercent
Conditions1414100.00
Logical1414100.00
Non-Logical00
Event00

 LINE       43
 EXPRESSION (h2d.a_mask[0] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT4,T1,T5

 LINE       44
 EXPRESSION (h2d.a_mask[1] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT4,T1,T5

 LINE       45
 EXPRESSION (h2d.a_mask[2] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT4,T1,T5

 LINE       46
 EXPRESSION (h2d.a_mask[3] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT4,T1,T5

 LINE       134
 EXPRESSION (h2d.a_valid && d2h.a_ready)
             -----1-----    -----2-----
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T2,T3
11CoveredT4,T1,T5

 LINE       150
 EXPRESSION (h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1))
             -----1-----    ----------------------2----------------------
-1--2-StatusTests
01CoveredT1,T7,T8
10CoveredT1,T2,T3
11CoveredT4,T1,T5

Branch Coverage for Module : sysrst_ctrl_csr_assert_fpv
Line No.TotalCoveredPercent
Branches 49 47 95.92
TERNARY 43 2 2 100.00
TERNARY 44 2 2 100.00
TERNARY 45 2 2 100.00
TERNARY 46 2 2 100.00
CASE 53 30 30 100.00
IF 102 11 9 81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv' or '../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 43 (h2d.a_mask[0]) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T1,T5,T6


LineNo. Expression -1-: 44 (h2d.a_mask[1]) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T1,T5,T6


LineNo. Expression -1-: 45 (h2d.a_mask[2]) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T1,T5,T7


LineNo. Expression -1-: 46 (h2d.a_mask[3]) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T1,T5,T7


LineNo. Expression -1-: 53 case (pend_trans[d2h.d_source].addr)

Branches:
-1-StatusTests
4 Covered T4,T1,T5
8 Covered T4,T1,T5
12 Covered T4,T1,T5
16 Covered T4,T1,T5
20 Covered T4,T1,T5
24 Covered T4,T1,T5
28 Covered T4,T1,T5
32 Covered T4,T1,T5
36 Covered T4,T1,T5
48 Covered T4,T1,T5
52 Covered T4,T1,T5
56 Covered T4,T1,T5
60 Covered T4,T1,T5
68 Covered T4,T1,T5
72 Covered T4,T1,T5
76 Covered T4,T1,T5
80 Covered T4,T1,T5
84 Covered T4,T1,T5
88 Covered T4,T1,T5
92 Covered T4,T1,T5
96 Covered T4,T1,T5
100 Covered T4,T1,T5
104 Covered T4,T1,T5
108 Covered T4,T1,T5
112 Covered T4,T1,T5
116 Covered T4,T1,T5
120 Covered T4,T1,T5
124 Covered T4,T1,T5
128 Covered T4,T1,T5
default Covered T4,T1,T5


LineNo. Expression -1-: 102 if ((!rst_ni)) -2-: 134 if ((h2d.a_valid && d2h.a_ready)) -3-: 136 if ((h2d.a_opcode inside {PutFullData, PutPartialData})) -4-: 139 if ((h2d.a_opcode == Get)) -5-: 143 if (d2h.d_valid) -6-: 144 if ((pend_trans[d2h.d_source].wr_pending == 1'b1)) -7-: 145 if ((!d2h.d_error)) -8-: 150 if ((h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1)))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
1 - - - - - - - Covered T4,T1,T5
0 1 1 - - - - - Covered T1,T2,T3
0 1 0 1 - - - - Covered T4,T1,T5
0 1 0 0 - - - - Not Covered
0 0 - - - - - - Covered T4,T1,T5
0 - - - 1 1 1 - Covered T1,T2,T3
0 - - - 1 1 0 - Not Covered
0 - - - 1 0 - - Covered T4,T1,T5
0 - - - 1 - - 1 Covered T4,T1,T5
0 - - - 1 - - 0 Covered T1,T7,T8
0 - - - 0 - - - Covered T4,T1,T5


Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
intr_enable_rd_A 2173815 0 0 0
pin_out_ctl_rd_A 2173815 0 0 0
pin_out_value_rd_A 2173815 0 0 0
ulp_ctl_rd_A 2173815 0 0 0


intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2173815 0 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2173815 0 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2173815 0 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2173815 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%