Module Definition
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Module : sysrst_ctrl_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.93 99.57 95.70 96.67 83.78


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.98 100.00 25.00 98.93 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_aon_tgl 80.30 100.00 90.91 50.00
u_auto_block_debounce_ctl_auto_block_enable 100.00 100.00 100.00 100.00
u_auto_block_debounce_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_auto_block_debounce_ctl_debounce_timer 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_auto_block_out_ctl_key0_out_sel 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key0_out_value 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key1_out_sel 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key1_out_value 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key2_out_sel 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key2_out_value 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00
u_com_det_ctl_0 100.00 100.00 100.00 100.00
u_com_det_ctl_0_cdc 92.70 100.00 93.33 94.12 83.33
u_com_det_ctl_1 100.00 100.00 100.00 100.00
u_com_det_ctl_1_cdc 92.70 100.00 93.33 94.12 83.33
u_com_det_ctl_2 100.00 100.00 100.00 100.00
u_com_det_ctl_2_cdc 92.70 100.00 93.33 94.12 83.33
u_com_det_ctl_3 100.00 100.00 100.00 100.00
u_com_det_ctl_3_cdc 92.70 100.00 93.33 94.12 83.33
u_com_out_ctl_0_bat_disable_0 100.00 100.00 100.00 100.00
u_com_out_ctl_0_cdc 92.70 100.00 93.33 94.12 83.33
u_com_out_ctl_0_ec_rst_0 100.00 100.00 100.00 100.00
u_com_out_ctl_0_interrupt_0 100.00 100.00 100.00 100.00
u_com_out_ctl_0_rst_req_0 100.00 100.00 100.00 100.00
u_com_out_ctl_1_bat_disable_1 100.00 100.00 100.00 100.00
u_com_out_ctl_1_cdc 92.70 100.00 93.33 94.12 83.33
u_com_out_ctl_1_ec_rst_1 100.00 100.00 100.00 100.00
u_com_out_ctl_1_interrupt_1 100.00 100.00 100.00 100.00
u_com_out_ctl_1_rst_req_1 100.00 100.00 100.00 100.00
u_com_out_ctl_2_bat_disable_2 100.00 100.00 100.00 100.00
u_com_out_ctl_2_cdc 92.70 100.00 93.33 94.12 83.33
u_com_out_ctl_2_ec_rst_2 100.00 100.00 100.00 100.00
u_com_out_ctl_2_interrupt_2 100.00 100.00 100.00 100.00
u_com_out_ctl_2_rst_req_2 100.00 100.00 100.00 100.00
u_com_out_ctl_3_bat_disable_3 100.00 100.00 100.00 100.00
u_com_out_ctl_3_cdc 92.70 100.00 93.33 94.12 83.33
u_com_out_ctl_3_ec_rst_3 100.00 100.00 100.00 100.00
u_com_out_ctl_3_interrupt_3 100.00 100.00 100.00 100.00
u_com_out_ctl_3_rst_req_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_ac_present_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_cdc 92.70 100.00 93.33 94.12 83.33
u_com_sel_ctl_0_key0_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_key1_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_key2_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_pwrb_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_ac_present_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_cdc 92.70 100.00 93.33 94.12 83.33
u_com_sel_ctl_1_key0_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_key1_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_key2_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_pwrb_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_ac_present_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_cdc 92.70 100.00 93.33 94.12 83.33
u_com_sel_ctl_2_key0_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_key1_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_key2_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_pwrb_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_ac_present_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_cdc 92.70 100.00 93.33 94.12 83.33
u_com_sel_ctl_3_key0_in_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_key1_in_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_key2_in_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_pwrb_in_sel_3 100.00 100.00 100.00 100.00
u_combo_intr_status_cdc 92.70 100.00 93.33 94.12 83.33
u_combo_intr_status_combo0_h2l 100.00 100.00 100.00
u_combo_intr_status_combo1_h2l 100.00 100.00 100.00
u_combo_intr_status_combo2_h2l 100.00 100.00 100.00
u_combo_intr_status_combo3_h2l 100.00 100.00 100.00
u_ec_rst_ctl 100.00 100.00 100.00 100.00
u_ec_rst_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_intr_enable 100.00 100.00 100.00 100.00
u_intr_state 100.00 100.00 100.00
u_intr_test 100.00 100.00
u_key_intr_ctl_ac_present_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_ac_present_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_key_intr_ctl_ec_rst_l_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_ec_rst_l_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_key0_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_key0_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_key1_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_key1_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_key2_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_key2_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_pwrb_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_pwrb_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_debounce_ctl 100.00 100.00 100.00 100.00
u_key_intr_debounce_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_key_intr_status_ac_present_h2l 100.00 100.00 100.00
u_key_intr_status_ac_present_l2h 100.00 100.00 100.00
u_key_intr_status_cdc 92.70 100.00 93.33 94.12 83.33
u_key_intr_status_ec_rst_l_h2l 100.00 100.00 100.00
u_key_intr_status_ec_rst_l_l2h 100.00 100.00 100.00
u_key_intr_status_key0_in_h2l 100.00 100.00 100.00
u_key_intr_status_key0_in_l2h 100.00 100.00 100.00
u_key_intr_status_key1_in_h2l 100.00 100.00 100.00
u_key_intr_status_key1_in_l2h 100.00 100.00 100.00
u_key_intr_status_key2_in_h2l 100.00 100.00 100.00
u_key_intr_status_key2_in_l2h 100.00 100.00 100.00
u_key_intr_status_pwrb_h2l 100.00 100.00 100.00
u_key_intr_status_pwrb_l2h 100.00 100.00 100.00
u_key_invert_ctl_ac_present 100.00 100.00 100.00 100.00
u_key_invert_ctl_bat_disable 100.00 100.00 100.00 100.00
u_key_invert_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_key_invert_ctl_key0_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_key0_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_key1_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_key1_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_key2_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_key2_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_lid_open 100.00 100.00 100.00 100.00
u_key_invert_ctl_pwrb_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_pwrb_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_z3_wakeup 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_bat_disable_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_bat_disable_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_pin_allowed_ctl_ec_rst_l_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_ec_rst_l_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_flash_wp_l_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_flash_wp_l_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key0_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key0_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key1_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key1_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key2_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key2_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_pwrb_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_pwrb_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_z3_wakeup_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_z3_wakeup_1 100.00 100.00 100.00 100.00
u_pin_in_value_ac_present 80.00 80.00 80.00
u_pin_in_value_ec_rst_l 80.00 80.00 80.00
u_pin_in_value_key0_in 80.00 80.00 80.00
u_pin_in_value_key1_in 80.00 80.00 80.00
u_pin_in_value_key2_in 80.00 80.00 80.00
u_pin_in_value_lid_open 80.00 80.00 80.00
u_pin_in_value_pwrb_in 80.00 80.00 80.00
u_pin_out_ctl_bat_disable 100.00 100.00 100.00 100.00
u_pin_out_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_pin_out_ctl_ec_rst_l 100.00 100.00 100.00 100.00
u_pin_out_ctl_flash_wp_l 100.00 100.00 100.00 100.00
u_pin_out_ctl_key0_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_key1_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_key2_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_pwrb_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_z3_wakeup 100.00 100.00 100.00 100.00
u_pin_out_value_bat_disable 100.00 100.00 100.00 100.00
u_pin_out_value_cdc 92.70 100.00 93.33 94.12 83.33
u_pin_out_value_ec_rst_l 100.00 100.00 100.00 100.00
u_pin_out_value_flash_wp_l 100.00 100.00 100.00 100.00
u_pin_out_value_key0_out 100.00 100.00 100.00 100.00
u_pin_out_value_key1_out 100.00 100.00 100.00 100.00
u_pin_out_value_key2_out 100.00 100.00 100.00 100.00
u_pin_out_value_pwrb_out 100.00 100.00 100.00 100.00
u_pin_out_value_z3_wakeup 100.00 100.00 100.00 100.00
u_reg_if 100.00 100.00 100.00 100.00 100.00
u_regwen 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_ulp_ac_debounce_ctl 100.00 100.00 100.00 100.00
u_ulp_ac_debounce_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_ulp_ctl 100.00 100.00 100.00 100.00
u_ulp_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_ulp_lid_debounce_ctl 100.00 100.00 100.00 100.00
u_ulp_lid_debounce_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_ulp_pwrb_debounce_ctl 100.00 100.00 100.00 100.00
u_ulp_pwrb_debounce_ctl_cdc 92.70 100.00 93.33 94.12 83.33
u_ulp_status 100.00 100.00 100.00
u_ulp_status_cdc 92.70 100.00 93.33 94.12 83.33
u_wkup_status 100.00 100.00 100.00
u_wkup_status_cdc 92.70 100.00 93.33 94.12 83.33


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_reg_top
Line No.TotalCoveredPercent
TOTAL347347100.00
ALWAYS6044100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS24322100.00
CONT_ASSIGN26911100.00
ALWAYS27922100.00
CONT_ASSIGN30511100.00
ALWAYS31522100.00
CONT_ASSIGN34111100.00
ALWAYS35122100.00
CONT_ASSIGN37711100.00
ALWAYS38622100.00
CONT_ASSIGN41211100.00
ALWAYS42122100.00
CONT_ASSIGN44711100.00
ALWAYS45622100.00
CONT_ASSIGN48211100.00
ALWAYS5031313100.00
CONT_ASSIGN54011100.00
ALWAYS5651717100.00
CONT_ASSIGN60611100.00
ALWAYS62299100.00
CONT_ASSIGN65511100.00
ALWAYS67199100.00
CONT_ASSIGN70411100.00
ALWAYS7251313100.00
CONT_ASSIGN76211100.00
ALWAYS77222100.00
CONT_ASSIGN79811100.00
ALWAYS80933100.00
CONT_ASSIGN83611100.00
ALWAYS85177100.00
CONT_ASSIGN88211100.00
ALWAYS89666100.00
CONT_ASSIGN92611100.00
ALWAYS94066100.00
CONT_ASSIGN97011100.00
ALWAYS98466100.00
CONT_ASSIGN101411100.00
ALWAYS102866100.00
CONT_ASSIGN105811100.00
ALWAYS106822100.00
CONT_ASSIGN109411100.00
ALWAYS110422100.00
CONT_ASSIGN113011100.00
ALWAYS114022100.00
CONT_ASSIGN116611100.00
ALWAYS117622100.00
CONT_ASSIGN120211100.00
ALWAYS121555100.00
CONT_ASSIGN124411100.00
ALWAYS125755100.00
CONT_ASSIGN128611100.00
ALWAYS129955100.00
CONT_ASSIGN132811100.00
ALWAYS134155100.00
CONT_ASSIGN137011100.00
ALWAYS138255100.00
CONT_ASSIGN141111100.00
ALWAYS14311313100.00
CONT_ASSIGN146811100.00
ALWAYS50173636100.00
CONT_ASSIGN505511100.00
ALWAYS505911100.00
CONT_ASSIGN509611100.00
CONT_ASSIGN509811100.00
CONT_ASSIGN509911100.00
CONT_ASSIGN510111100.00
CONT_ASSIGN510211100.00
CONT_ASSIGN510411100.00
CONT_ASSIGN510511100.00
CONT_ASSIGN510711100.00
CONT_ASSIGN510811100.00
CONT_ASSIGN511011100.00
CONT_ASSIGN511111100.00
CONT_ASSIGN511311100.00
CONT_ASSIGN511511100.00
CONT_ASSIGN511711100.00
CONT_ASSIGN511911100.00
CONT_ASSIGN512111100.00
CONT_ASSIGN512311100.00
CONT_ASSIGN512511100.00
CONT_ASSIGN513811100.00
CONT_ASSIGN515511100.00
CONT_ASSIGN516411100.00
CONT_ASSIGN517311100.00
CONT_ASSIGN518611100.00
CONT_ASSIGN518811100.00
CONT_ASSIGN519111100.00
CONT_ASSIGN519811100.00
CONT_ASSIGN520411100.00
CONT_ASSIGN521011100.00
CONT_ASSIGN521611100.00
CONT_ASSIGN522211100.00
CONT_ASSIGN522411100.00
CONT_ASSIGN522611100.00
CONT_ASSIGN522811100.00
CONT_ASSIGN523011100.00
CONT_ASSIGN523511100.00
CONT_ASSIGN524011100.00
CONT_ASSIGN524511100.00
CONT_ASSIGN525011100.00
CONT_ASSIGN525511100.00
ALWAYS52714343100.00
CONT_ASSIGN540211100.00
ALWAYS54043131100.00
CONT_ASSIGN550611100.00
CONT_ASSIGN550711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
63 1 1
MISSING_ELSE
69 1 1
119 1 1
120 1 1
243 1 1
244 1 1
269 1 1
279 1 1
280 1 1
305 1 1
315 1 1
316 1 1
341 1 1
351 1 1
352 1 1
377 1 1
386 1 1
387 1 1
412 1 1
421 1 1
422 1 1
447 1 1
456 1 1
457 1 1
482 1 1
503 1 1
504 1 1
505 1 1
506 1 1
507 1 1
508 1 1
509 1 1
510 1 1
511 1 1
512 1 1
513 1 1
514 1 1
515 1 1
540 1 1
565 1 1
566 1 1
567 1 1
568 1 1
569 1 1
570 1 1
571 1 1
572 1 1
573 1 1
574 1 1
575 1 1
576 1 1
577 1 1
578 1 1
579 1 1
580 1 1
581 1 1
606 1 1
622 1 1
623 1 1
624 1 1
625 1 1
626 1 1
627 1 1
628 1 1
629 1 1
630 1 1
655 1 1
671 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
678 1 1
679 1 1
704 1 1
725 1 1
726 1 1
727 1 1
728 1 1
729 1 1
730 1 1
731 1 1
732 1 1
733 1 1
734 1 1
735 1 1
736 1 1
737 1 1
762 1 1
772 1 1
773 1 1
798 1 1
809 1 1
810 1 1
811 1 1
836 1 1
851 1 1
852 1 1
853 1 1
854 1 1
855 1 1
856 1 1
857 1 1
882 1 1
896 1 1
897 1 1
898 1 1
899 1 1
900 1 1
901 1 1
926 1 1
940 1 1
941 1 1
942 1 1
943 1 1
944 1 1
945 1 1
970 1 1
984 1 1
985 1 1
986 1 1
987 1 1
988 1 1
989 1 1
1014 1 1
1028 1 1
1029 1 1
1030 1 1
1031 1 1
1032 1 1
1033 1 1
1058 1 1
1068 1 1
1069 1 1
1094 1 1
1104 1 1
1105 1 1
1130 1 1
1140 1 1
1141 1 1
1166 1 1
1176 1 1
1177 1 1
1202 1 1
1215 1 1
1216 1 1
1217 1 1
1218 1 1
1219 1 1
1244 1 1
1257 1 1
1258 1 1
1259 1 1
1260 1 1
1261 1 1
1286 1 1
1299 1 1
1300 1 1
1301 1 1
1302 1 1
1303 1 1
1328 1 1
1341 1 1
1342 1 1
1343 1 1
1344 1 1
1345 1 1
1370 1 1
1382 1 1
1383 1 1
1384 1 1
1385 1 1
1386 1 1
1411 1 1
1431 1 1
1432 1 1
1433 1 1
1434 1 1
1435 1 1
1436 1 1
1437 1 1
1438 1 1
1439 1 1
1440 1 1
1441 1 1
1442 1 1
1443 1 1
1468 1 1
5017 1 1
5018 1 1
5019 1 1
5020 1 1
5021 1 1
5022 1 1
5023 1 1
5024 1 1
5025 1 1
5026 1 1
5027 1 1
5028 1 1
5029 1 1
5030 1 1
5031 1 1
5032 1 1
5033 1 1
5034 1 1
5035 1 1
5036 1 1
5037 1 1
5038 1 1
5039 1 1
5040 1 1
5041 1 1
5042 1 1
5043 1 1
5044 1 1
5045 1 1
5046 1 1
5047 1 1
5048 1 1
5049 1 1
5050 1 1
5051 1 1
5052 1 1
5055 1 1
5059 1 1
5096 1 1
5098 1 1
5099 1 1
5101 1 1
5102 1 1
5104 1 1
5105 1 1
5107 1 1
5108 1 1
5110 1 1
5111 1 1
5113 1 1
5115 1 1
5117 1 1
5119 1 1
5121 1 1
5123 1 1
5125 1 1
5138 1 1
5155 1 1
5164 1 1
5173 1 1
5186 1 1
5188 1 1
5191 1 1
5198 1 1
5204 1 1
5210 1 1
5216 1 1
5222 1 1
5224 1 1
5226 1 1
5228 1 1
5230 1 1
5235 1 1
5240 1 1
5245 1 1
5250 1 1
5255 1 1
5271 1 1
5272 1 1
5274 1 1
5278 1 1
5282 1 1
5286 1 1
5290 1 1
5294 1 1
5297 1 1
5300 1 1
5303 1 1
5306 1 1
5309 1 1
5312 1 1
5315 1 1
5318 1 1
5321 1 1
5324 1 1
5327 1 1
5328 1 1
5329 1 1
5330 1 1
5331 1 1
5332 1 1
5333 1 1
5337 1 1
5340 1 1
5343 1 1
5346 1 1
5349 1 1
5352 1 1
5355 1 1
5358 1 1
5361 1 1
5364 1 1
5367 1 1
5370 1 1
5373 1 1
5376 1 1
5379 1 1
5382 1 1
5385 1 1
5388 1 1
5402 1 1
5404 1 1
5405 1 1
5407 1 1
5410 1 1
5413 1 1
5416 1 1
5419 1 1
5422 1 1
5425 1 1
5428 1 1
5431 1 1
5434 1 1
5437 1 1
5440 1 1
5443 1 1
5446 1 1
5449 1 1
5452 1 1
5455 1 1
5458 1 1
5461 1 1
5464 1 1
5467 1 1
5470 1 1
5473 1 1
5476 1 1
5479 1 1
5482 1 1
5485 1 1
5488 1 1
5491 1 1
5506 1 1
5507 1 1


Cond Coverage for Module : sysrst_ctrl_reg_top
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       5055
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       5055
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT1,T2,T3
10CoveredT4,T1,T5

Branch Coverage for Module : sysrst_ctrl_reg_top
Line No.TotalCoveredPercent
Branches 71 71 100.00
TERNARY 5055 2 2 100.00
IF 60 3 3 100.00
CASE 5272 36 36 100.00
CASE 5405 30 30 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 5055 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 60 if ((!rst_ni)) -2-: 62 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Covered T15,T21,T40
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 5272 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T1,T5
addr_hit[1] Covered T4,T1,T5
addr_hit[2] Covered T4,T1,T5
addr_hit[3] Covered T4,T1,T5
addr_hit[4] Covered T4,T1,T5
addr_hit[5] Covered T4,T1,T5
addr_hit[6] Covered T4,T1,T5
addr_hit[7] Covered T4,T1,T5
addr_hit[8] Covered T4,T1,T5
addr_hit[9] Covered T4,T1,T5
addr_hit[10] Covered T4,T1,T5
addr_hit[11] Covered T4,T1,T5
addr_hit[12] Covered T4,T1,T5
addr_hit[13] Covered T4,T1,T5
addr_hit[14] Covered T4,T1,T5
addr_hit[15] Covered T4,T1,T5
addr_hit[16] Covered T4,T1,T5
addr_hit[17] Covered T4,T1,T5
addr_hit[18] Covered T4,T1,T5
addr_hit[19] Covered T4,T1,T5
addr_hit[20] Covered T4,T1,T5
addr_hit[21] Covered T4,T1,T5
addr_hit[22] Covered T4,T1,T5
addr_hit[23] Covered T4,T1,T5
addr_hit[24] Covered T4,T1,T5
addr_hit[25] Covered T4,T1,T5
addr_hit[26] Covered T4,T1,T5
addr_hit[27] Covered T4,T1,T5
addr_hit[28] Covered T4,T1,T5
addr_hit[29] Covered T4,T1,T5
addr_hit[30] Covered T4,T1,T5
addr_hit[31] Covered T4,T1,T5
addr_hit[32] Covered T4,T1,T5
addr_hit[33] Covered T4,T1,T5
addr_hit[34] Covered T4,T1,T5
default Covered T4,T1,T5


LineNo. Expression -1-: 5405 case (1'b1)

Branches:
-1-StatusTests
addr_hit[5] Covered T4,T1,T5
addr_hit[6] Covered T4,T1,T5
addr_hit[7] Covered T4,T1,T5
addr_hit[8] Covered T4,T1,T5
addr_hit[9] Covered T4,T1,T5
addr_hit[10] Covered T4,T1,T5
addr_hit[11] Covered T4,T1,T5
addr_hit[12] Covered T4,T1,T5
addr_hit[13] Covered T4,T1,T5
addr_hit[14] Covered T4,T1,T5
addr_hit[15] Covered T4,T1,T5
addr_hit[17] Covered T4,T1,T5
addr_hit[18] Covered T4,T1,T5
addr_hit[19] Covered T4,T1,T5
addr_hit[20] Covered T4,T1,T5
addr_hit[21] Covered T4,T1,T5
addr_hit[22] Covered T4,T1,T5
addr_hit[23] Covered T4,T1,T5
addr_hit[24] Covered T4,T1,T5
addr_hit[25] Covered T4,T1,T5
addr_hit[26] Covered T4,T1,T5
addr_hit[27] Covered T4,T1,T5
addr_hit[28] Covered T4,T1,T5
addr_hit[29] Covered T4,T1,T5
addr_hit[30] Covered T4,T1,T5
addr_hit[31] Covered T4,T1,T5
addr_hit[32] Covered T4,T1,T5
addr_hit[33] Covered T4,T1,T5
addr_hit[34] Covered T4,T1,T5
default Covered T4,T1,T5


Assert Coverage for Module : sysrst_ctrl_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 41647230 73808 0 0
reAfterRv 41647230 73806 0 0
rePulse 41647230 44005 0 0
wePulse 41647230 29801 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 41647230 73808 0 0
T1 41487 43 0 0
T4 11720 1 0 0
T5 6927 22 0 0
T6 1600 5 0 0
T7 13925 26 0 0
T8 2273 11 0 0
T9 5580 29 0 0
T10 3363 1 0 0
T11 12090 47 0 0
T12 24758 49 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 41647230 73806 0 0
T1 41487 43 0 0
T4 11720 1 0 0
T5 6927 22 0 0
T6 1600 5 0 0
T7 13925 26 0 0
T8 2273 11 0 0
T9 5580 29 0 0
T10 3363 1 0 0
T11 12090 47 0 0
T12 24758 49 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 41647230 44005 0 0
T1 41487 21 0 0
T4 11720 1 0 0
T5 6927 22 0 0
T6 1600 5 0 0
T7 13925 26 0 0
T8 2273 11 0 0
T9 5580 29 0 0
T10 3363 1 0 0
T11 12090 47 0 0
T12 24758 49 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 41647230 29801 0 0
T1 41487 22 0 0
T2 40590 22 0 0
T3 41474 22 0 0
T25 20472 22 0 0
T26 21270 22 0 0
T27 32529 22 0 0
T28 10498 22 0 0
T29 20495 22 0 0
T30 21143 22 0 0
T31 26783 22 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%