60c1f1277| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 16 | 20 | 80.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | TOTAL | 151 | 205 | 73.66 | |
| V2 | combo_detect | sysrst_ctrl_combo_detect | 0 | 0 | -- |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 0 | 0 | -- |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 0 | 0 | -- |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_override_test | 0 | 0 | -- |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 0 | 0 | -- |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 0 | 0 | -- |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 0 | 0 | -- |
| V2 | alert_test | sysrst_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 50 | 0.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 16 | 20 | 80.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 16 | 20 | 80.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 139 | 190 | 73.16 | |
| V2S | tl_intg_err | sysrst_ctrl_tl_intg_err | 17 | 20 | 85.00 |
| V2S | TOTAL | 17 | 20 | 85.00 | |
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| Unmapped tests | sysrst_ctrl_stress_all | 0 | 50 | 0.00 | |
| TOTAL | 307 | 515 | 59.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 6 | 75.00 |
| V2 | 12 | 5 | 3 | 25.00 |
| V2S | 1 | 1 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.81 | 99.57 | 82.92 | 98.98 | -- | 92.78 | 91.55 | 79.06 |
UVM_WARNING [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.sysrst_ctrl_stress_all.4000478367
Line 298, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.sysrst_ctrl_stress_all.3987483754
Line 298, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.sysrst_ctrl_stress_all_with_rand_reset.4242252389
Line 299, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 8034273 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 8034273 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.sysrst_ctrl_stress_all_with_rand_reset.3041625999
Line 299, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 8033891 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 8033891 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (sysrst_ctrl_scoreboard.sv:95) scoreboard [scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_* has 50 failures:
0.sysrst_ctrl_combo_detect_ec_rst.1609661981
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/out/run.log
UVM_ERROR @ 8257851 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_ERROR @ 8267851 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_INFO @ 8267851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sysrst_ctrl_combo_detect_ec_rst.3660690555
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/out/run.log
UVM_ERROR @ 8288997 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_ERROR @ 8328997 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_INFO @ 8328997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:460) [sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (* [*] vs *xX [x]) has 50 failures:
0.sysrst_ctrl_intr_test.1596446169
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/out/run.log
UVM_ERROR @ 8115488 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8160432 ps: (cip_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 2/6
UVM_ERROR @ 8272792 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8272792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sysrst_ctrl_intr_test.3012964945
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/out/run.log
UVM_ERROR @ 9184364 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 9324364 ps: (cip_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 2/3
UVM_ERROR @ 10164364 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 10164364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:476) [sysrst_ctrl_common_vseq] Check failed data == * (* [*] vs * [*]) has 5 failures:
0.sysrst_ctrl_csr_rw.791463997
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/out/run.log
UVM_ERROR @ 29872459 ps: (cip_base_vseq.sv:476) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed data == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 62497680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sysrst_ctrl_csr_rw.221732527
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/out/run.log
UVM_ERROR @ 46685722 ps: (cip_base_vseq.sv:476) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed data == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 77224490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
15.sysrst_ctrl_same_csr_outstanding.1759131896
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/out/run.log
UVM_ERROR @ 2046843516 ps: (cip_base_vseq.sv:476) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed data == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2061718358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.com_det_ctl_*.detection_timer_* has 1 failures:
0.sysrst_ctrl_tl_intg_err.332489150
Line 373, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/out/run.log
UVM_ERROR @ 16178311997 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (2930734746 [0xaeaf769a] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0
UVM_INFO @ 16178368817 ps: (cip_tl_seq_item.sv:106) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below:
a_addr: 0xe3534434
-> 0xa35344b4 a_opcode: 0x4
-> 0x4 a_mask: 0xf
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.ec_rst_ctl has 1 failures:
1.sysrst_ctrl_tl_intg_err.4018086190
Line 434, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/out/run.log
UVM_ERROR @ 34363417542 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (7049 [0x1b89] vs 2000 [0x7d0]) Regname: sysrst_ctrl_reg_block.ec_rst_ctl
UVM_INFO @ 34376428375 ps: (cip_tl_seq_item.sv:106) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below:
a_addr: 0x1a8d5144
-> 0x1a8d5154 a_opcode: 0x4
-> 0x4 a_mask: 0xf
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable has 1 failures:
8.sysrst_ctrl_tl_intg_err.3398352052
Line 372, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/out/run.log
UVM_ERROR @ 14141823213 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable
UVM_ERROR @ 14142884429 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.com_out_ctl_0
UVM_INFO @ 14142884429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---