Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total487010
Category 0487010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total487010
Severity 0487010


Summary for Assertions
NUMBERPERCENT
Total Number487100.00
Uncovered346.98
Success45393.02
Failure00.00
Incomplete81.64
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered880.00
All Matches220.00
First Matches220.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.sysrst_ctrl_csr_assert.intr_enable_rd_A 002122381000
tb.dut.sysrst_ctrl_csr_assert.pin_out_ctl_rd_A 002122381000
tb.dut.sysrst_ctrl_csr_assert.pin_out_value_rd_A 002122381000
tb.dut.sysrst_ctrl_csr_assert.ulp_ctl_rd_A 002122381000
tb.dut.u_reg.u_aon_tgl.SyncReqAckHoldReq 00304535000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000
tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync.SyncReqAckHoldReq 0060874341000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertKnownO_A 002122381211086800
tb.dut.BatOEnKnown 002122381211086800
tb.dut.BatOKnown 002122381211086800
tb.dut.ECRSTOEnKnown 002122381211086800
tb.dut.ECRSTOKnown 002122381211086800
tb.dut.FlashWpOEnKnown 002122381211086800
tb.dut.FlashWpOKnown 002122381211086800
tb.dut.IntrSysRstCtrlOKnown 002122381211086800
tb.dut.Key0OEnKnown 002122381211086800
tb.dut.Key0OKnown 002122381211086800
tb.dut.Key1OEnKnown 002122381211086800
tb.dut.Key1OKnown 002122381211086800
tb.dut.Key2OEnKnown 002122381211086800
tb.dut.Key2OKnown 002122381211086800
tb.dut.OTRstOKnown 002122381211086800
tb.dut.OTWkOKnown 002122381211086800
tb.dut.PwrbOEnKnown 002122381211086800
tb.dut.PwrbOKnown 002122381211086800
tb.dut.TlOAReadyKnown 002122381211086800
tb.dut.TlODValidKnown 002122381211086800
tb.dut.Z3WakeupOEnKnown 002122381211086800
tb.dut.Z3WwakupOKnown 002122381211086800
tb.dut.tlul_assert_device.aKnown_A 00212238174114500
tb.dut.tlul_assert_device.aKnown_AKnownEnable 002122381211086800
tb.dut.tlul_assert_device.aReadyKnown_A 002122381211086800
tb.dut.tlul_assert_device.dKnown_A 002122381704200
tb.dut.tlul_assert_device.dKnown_AKnownEnable 002122381211086800
tb.dut.tlul_assert_device.dReadyKnown_A 002122381211086800
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0015015000
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tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0015015000
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 002122473110000
tb.dut.tlul_assert_device.gen_device.addrSizeAligned_M 00212247374114500
tb.dut.tlul_assert_device.gen_device.contigMask_M 00212247374057800
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 002122473493300
tb.dut.tlul_assert_device.gen_device.legalAOpcode_M 00212247374114500
tb.dut.tlul_assert_device.gen_device.legalAParam_M 00212247374114500
tb.dut.tlul_assert_device.gen_device.legalDParam_A 002122473704200
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 00212247374114500
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 002122473704200
tb.dut.tlul_assert_device.gen_device.respOpcode_A 002122473704200
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 002122473704200
tb.dut.tlul_assert_device.gen_device.sizeGTEMask_M 00212247374114500
tb.dut.tlul_assert_device.gen_device.sizeMatchesMask_M 00212247374114500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0015015000
tb.dut.u_reg.en2addrHit 00608743418082700
tb.dut.u_reg.reAfterRv 00608743418082300
tb.dut.u_reg.rePulse 00608743414870500
tb.dut.u_reg.u_aon_tgl.SyncReqAckAckNeedsReq 00608743411396700
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.HungHandShake_A 006087434192000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.ReqTimeout_A 0030453592100
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453592100
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.HungHandShake_A 006087434189300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.ReqTimeout_A 0030453589400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453589400
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0031531500
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_det_ctl_0_cdc.HungHandShake_A 006087434191600
tb.dut.u_reg.u_com_det_ctl_0_cdc.ReqTimeout_A 0030453591800
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453591800
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_det_ctl_1_cdc.HungHandShake_A 006087434192900
tb.dut.u_reg.u_com_det_ctl_1_cdc.ReqTimeout_A 0030453593000
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453593000
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_det_ctl_2_cdc.HungHandShake_A 006087434190501
tb.dut.u_reg.u_com_det_ctl_2_cdc.ReqTimeout_A 0030453590701
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453590700
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_det_ctl_3_cdc.HungHandShake_A 006087434194501
tb.dut.u_reg.u_com_det_ctl_3_cdc.ReqTimeout_A 0030453594601
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453594600
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_out_ctl_0_cdc.HungHandShake_A 006087434192801
tb.dut.u_reg.u_com_out_ctl_0_cdc.ReqTimeout_A 0030453592901
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453592900
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_out_ctl_1_cdc.HungHandShake_A 006087434192600
tb.dut.u_reg.u_com_out_ctl_1_cdc.ReqTimeout_A 0030453592700
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453592700
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_out_ctl_2_cdc.HungHandShake_A 006087434192400
tb.dut.u_reg.u_com_out_ctl_2_cdc.ReqTimeout_A 0030453592500
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453592500
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_out_ctl_3_cdc.HungHandShake_A 006087434191700
tb.dut.u_reg.u_com_out_ctl_3_cdc.ReqTimeout_A 0030453591800
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453591800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_sel_ctl_0_cdc.HungHandShake_A 006087434192600
tb.dut.u_reg.u_com_sel_ctl_0_cdc.ReqTimeout_A 0030453592800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453592800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.HungHandShake_A 006087434195300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.ReqTimeout_A 0030453595400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453595400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.HungHandShake_A 006087434191400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.ReqTimeout_A 0030453591500
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453591500
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.HungHandShake_A 006087434190800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.ReqTimeout_A 0030453590900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453590900
tb.dut.u_reg.u_combo_intr_status_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_combo_intr_status_cdc.HungHandShake_A 006087434146500
tb.dut.u_reg.u_combo_intr_status_cdc.ReqTimeout_A 0030453546600
tb.dut.u_reg.u_combo_intr_status_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453546600
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_ec_rst_ctl_cdc.HungHandShake_A 006087434190700
tb.dut.u_reg.u_ec_rst_ctl_cdc.ReqTimeout_A 0030453590800
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453590800
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_key_intr_ctl_cdc.HungHandShake_A 006087434190000
tb.dut.u_reg.u_key_intr_ctl_cdc.ReqTimeout_A 0030453590100
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453590100
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.HungHandShake_A 006087434191400
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.ReqTimeout_A 0030453591500
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453591500
tb.dut.u_reg.u_key_intr_status_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_key_intr_status_cdc.HungHandShake_A 006087434147100
tb.dut.u_reg.u_key_intr_status_cdc.ReqTimeout_A 0030453547200
tb.dut.u_reg.u_key_intr_status_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453547200
tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_key_invert_ctl_cdc.HungHandShake_A 0060874341194400
tb.dut.u_reg.u_key_invert_ctl_cdc.ReqTimeout_A 00304535194500
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 00304535194500
tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_pin_allowed_ctl_cdc.HungHandShake_A 006087434199800
tb.dut.u_reg.u_pin_allowed_ctl_cdc.ReqTimeout_A 0030453599900
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453599900
tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_pin_out_ctl_cdc.HungHandShake_A 006087434195000
tb.dut.u_reg.u_pin_out_ctl_cdc.ReqTimeout_A 0030453595100
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453595100
tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_pin_out_value_cdc.HungHandShake_A 006087434193300
tb.dut.u_reg.u_pin_out_value_cdc.ReqTimeout_A 0030453593400
tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453593400
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0031531500
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0031531500
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0031531500
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0031531500
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.HungHandShake_A 006087434192200
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.ReqTimeout_A 0030453592400
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453592400
tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_ulp_ctl_cdc.HungHandShake_A 006087434194000
tb.dut.u_reg.u_ulp_ctl_cdc.ReqTimeout_A 0030453594100
tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453594100
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.HungHandShake_A 006087434190300
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.ReqTimeout_A 0030453590400
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453590400
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.HungHandShake_A 006087434191400
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.ReqTimeout_A 0030453591600
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453591600
tb.dut.u_reg.u_ulp_status_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_ulp_status_cdc.HungHandShake_A 006087434150300
tb.dut.u_reg.u_ulp_status_cdc.ReqTimeout_A 0030453550400
tb.dut.u_reg.u_ulp_status_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453550400
tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A 003045355395300
tb.dut.u_reg.u_wkup_status_cdc.HungHandShake_A 006087434149501
tb.dut.u_reg.u_wkup_status_cdc.ReqTimeout_A 0030453549701
tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A 00608743416077348400
tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq 0030453549700
tb.dut.u_reg.wePulse 00608743413211800

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_reg.u_com_det_ctl_2_cdc.HungHandShake_A 006087434190501
tb.dut.u_reg.u_com_det_ctl_2_cdc.ReqTimeout_A 0030453590701
tb.dut.u_reg.u_com_det_ctl_3_cdc.HungHandShake_A 006087434194501
tb.dut.u_reg.u_com_det_ctl_3_cdc.ReqTimeout_A 0030453594601
tb.dut.u_reg.u_com_out_ctl_0_cdc.HungHandShake_A 006087434192801
tb.dut.u_reg.u_com_out_ctl_0_cdc.ReqTimeout_A 0030453592901
tb.dut.u_reg.u_wkup_status_cdc.HungHandShake_A 006087434149501
tb.dut.u_reg.u_wkup_status_cdc.ReqTimeout_A 0030453549701


Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 002122473000
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 002122473000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 002122473000
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 002122473000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 002122473000
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 002122473000
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002122473000
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 002122473000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00212247373843738430
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00212247317621762150

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 00212247373843738430
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 00212247317621762150

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