Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_sync_reqack
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_aon_tgl 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00



Module Instance : tb.dut.u_reg.u_aon_tgl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ec_rst_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_ac_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_lid_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_pwrb_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_wkup_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_invert_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_pin_allowed_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_pin_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_pin_out_value_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_intr_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_intr_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_auto_block_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_auto_block_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_combo_intr_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_intr_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 69705856 40065 0 0
SyncReqAckHoldReq 1765660424 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 69705856 40065 0 0
T1 15502 22 0 0
T2 21080 21 0 0
T3 21301 21 0 0
T4 10893 11 0 0
T7 11411 6 0 0
T8 3866 8 0 0
T9 11592 6 0 0
T10 11752 6 0 0
T11 11773 6 0 0
T12 4919 6 0 0
T13 66765 150 0 0
T14 66855 144 0 0
T15 6330 30 0 0
T16 127365 299 0 0
T17 6120 27 0 0
T18 12060 71 0 0
T19 11670 72 0 0
T20 128490 290 0 0
T21 127260 291 0 0
T22 139160 1781 0 0
T23 4453 10 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1765660424 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_aon_tgl
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_aon_tgl
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_aon_tgl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 60874341 13967 0 0
SyncReqAckHoldReq 304535 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 13967 0 0
T1 15502 22 0 0
T2 21080 21 0 0
T3 21301 21 0 0
T4 10893 11 0 0
T7 11411 6 0 0
T8 3866 8 0 0
T9 11592 6 0 0
T10 11752 6 0 0
T11 11773 6 0 0
T12 4919 6 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 908 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 908 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 3 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 924 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 924 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 19 0 0
T17 408 2 0 0
T18 804 11 0 0
T19 778 3 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 904 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 904 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 5 0 0
T19 778 12 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 916 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 916 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 7 0 0
T19 778 3 0 0
T20 8566 18 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 941 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 941 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 19 0 0
T17 408 2 0 0
T18 804 10 0 0
T19 778 1 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 504 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 504 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T19 778 7 0 0
T20 8566 17 0 0
T21 8484 20 0 0
T23 4453 10 0 0
T24 409 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 497 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 497 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 5 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T23 4453 10 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 1945 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 1945 0 0
T1 485 20 0 0
T2 483 20 0 0
T3 484 20 0 0
T25 482 20 0 0
T26 482 20 0 0
T27 484 20 0 0
T28 481 20 0 0
T29 482 20 0 0
T30 484 20 0 0
T31 483 20 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 999 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 999 0 0
T1 485 1 0 0
T2 483 1 0 0
T3 484 1 0 0
T25 482 1 0 0
T26 482 1 0 0
T27 484 1 0 0
T28 481 1 0 0
T29 482 1 0 0
T30 484 1 0 0
T31 483 1 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 951 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 951 0 0
T1 485 1 0 0
T2 483 1 0 0
T3 484 1 0 0
T25 482 1 0 0
T26 482 1 0 0
T27 484 1 0 0
T28 481 1 0 0
T29 482 1 0 0
T30 484 1 0 0
T31 483 1 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 934 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 934 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 9 0 0
T19 778 9 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 901 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 901 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 4 0 0
T19 778 4 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 915 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 915 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 5 0 0
T20 8566 17 0 0
T21 8484 20 0 0
T22 9940 128 0 0
T23 4453 10 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 921 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 921 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 1 0 0
T18 804 6 0 0
T19 778 4 0 0
T20 8566 18 0 0
T21 8484 19 0 0
T22 9940 126 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 894 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 894 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 2 0 0
T20 8566 20 0 0
T21 8484 17 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 928 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 928 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 13 0 0
T19 778 4 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 954 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 954 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 19 0 0
T17 408 2 0 0
T18 804 8 0 0
T19 778 5 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 915 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 915 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 6 0 0
T19 778 2 0 0
T20 8566 18 0 0
T21 8484 20 0 0
T22 9940 126 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 909 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 909 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 7 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 918 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 918 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 12 0 0
T19 778 10 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 930 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 930 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 5 0 0
T20 8566 20 0 0
T21 8484 18 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 907 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 907 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 4 0 0
T20 8566 19 0 0
T21 8484 19 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 946 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 946 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 2 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 929 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 929 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 1 0 0
T18 804 8 0 0
T19 778 6 0 0
T20 8566 19 0 0
T21 8484 19 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 927 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 927 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 5 0 0
T19 778 6 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 925 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 925 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 2 0 0
T20 8566 20 0 0
T21 8484 19 0 0
T22 9940 128 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 918 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 918 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 2 0 0
T19 778 7 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 126 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 466 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 466 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 1 0 0
T18 804 1 0 0
T19 778 6 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T23 4453 10 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 304535 472 0 0
SyncReqAckHoldReq 60874341 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 472 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 2 0 0
T19 778 8 0 0
T20 8566 19 0 0
T21 8484 19 0 0
T23 4453 10 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%