Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_status_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_wkup_status_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_intr_status_cdc 98.33 100.00 93.33 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 8831515 1564637 0 0
HungHandShake_A 1765355889 26063 0 4
ReqTimeout_A 8831515 26098 0 4
SrcBusyKnown_A 1765355889 1762431036 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8831515 1564637 0 0
T1 14065 2465 0 0
T2 14007 2407 0 0
T3 14036 2436 0 0
T4 12876 1276 0 0
T7 12238 638 0 0
T8 12441 841 0 0
T9 12238 638 0 0
T10 12238 638 0 0
T11 12238 638 0 0
T12 12296 696 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1765355889 26063 0 4
T1 15502 20 0 0
T2 21080 20 0 0
T3 21301 20 0 0
T13 18479723 190 0 0
T14 3855271 184 0 0
T15 55784 38 0 0
T16 4612706 379 0 0
T17 90592 35 0 0
T18 3814060 85 0 1
T19 1707444 87 0 0
T20 18622717 366 0 0
T21 7681377 370 0 0
T22 7785490 2164 0 0
T23 304074 30 0 0
T25 34171 20 0 0
T26 32501 20 0 0
T27 12772 20 0 0
T28 41123 20 0 0
T29 41624 20 0 0
T30 10312 20 0 0
T31 21039 20 0 0
T35 0 0 0 1
T36 0 0 0 1
T37 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8831515 26098 0 4
T1 485 20 0 0
T2 483 20 0 0
T3 484 20 0 0
T13 84569 190 0 0
T14 84683 184 0 0
T15 8018 38 0 0
T16 161329 379 0 0
T17 7752 35 0 0
T18 15276 85 0 1
T19 14004 87 0 0
T20 162754 366 0 0
T21 161196 370 0 0
T22 168980 2164 0 0
T23 13359 30 0 0
T25 482 20 0 0
T26 482 20 0 0
T27 484 20 0 0
T28 481 20 0 0
T29 482 20 0 0
T30 484 20 0 0
T31 483 20 0 0
T35 0 0 0 1
T36 0 0 0 1
T37 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1765355889 1762431036 0 0
T1 449558 447702 0 0
T2 611320 608652 0 0
T3 617729 616076 0 0
T4 315897 313113 0 0
T7 330919 328425 0 0
T8 112114 110664 0 0
T9 336168 333355 0 0
T10 340808 339039 0 0
T11 341417 338546 0 0
T12 142651 140911 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 907 0 0
ReqTimeout_A 304535 908 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 907 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 3 0 0
T19 94858 3 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 128 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 908 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 3 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 922 0 0
ReqTimeout_A 304535 924 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 922 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 19 0 0
T17 4768 2 0 0
T18 200740 11 0 0
T19 94858 3 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 924 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 19 0 0
T17 408 2 0 0
T18 804 11 0 0
T19 778 3 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 903 0 0
ReqTimeout_A 304535 904 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 903 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 5 0 0
T19 94858 12 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 904 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 5 0 0
T19 778 12 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 914 0 0
ReqTimeout_A 304535 916 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 914 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 7 0 0
T19 94858 3 0 0
T20 980143 18 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 916 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 7 0 0
T19 778 3 0 0
T20 8566 18 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 940 0 0
ReqTimeout_A 304535 941 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 940 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 19 0 0
T17 4768 2 0 0
T18 200740 10 0 0
T19 94858 1 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 128 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 941 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 19 0 0
T17 408 2 0 0
T18 804 10 0 0
T19 778 1 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 503 0 0
ReqTimeout_A 304535 504 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 503 0 0
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T19 94858 7 0 0
T20 980143 17 0 0
T21 404283 20 0 0
T23 101358 10 0 0
T24 5168 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 504 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T19 778 7 0 0
T20 8566 17 0 0
T21 8484 20 0 0
T23 4453 10 0 0
T24 409 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 495 0 1
ReqTimeout_A 304535 497 0 1
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 495 0 1
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 3 0 0
T19 94858 5 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T23 101358 10 0 0
T36 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 497 0 1
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 5 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T23 4453 10 0 0
T36 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 1944 0 0
ReqTimeout_A 304535 1945 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 1944 0 0
T1 15502 20 0 0
T2 21080 20 0 0
T3 21301 20 0 0
T25 34171 20 0 0
T26 32501 20 0 0
T27 12772 20 0 0
T28 41123 20 0 0
T29 41624 20 0 0
T30 10312 20 0 0
T31 21039 20 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 1945 0 0
T1 485 20 0 0
T2 483 20 0 0
T3 484 20 0 0
T25 482 20 0 0
T26 482 20 0 0
T27 484 20 0 0
T28 481 20 0 0
T29 482 20 0 0
T30 484 20 0 0
T31 483 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 998 0 0
ReqTimeout_A 304535 999 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 998 0 0
T1 15502 1 0 0
T2 21080 1 0 0
T3 21301 1 0 0
T25 34171 1 0 0
T26 32501 1 0 0
T27 12772 1 0 0
T28 41123 1 0 0
T29 41624 1 0 0
T30 10312 1 0 0
T31 21039 1 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 999 0 0
T1 485 1 0 0
T2 483 1 0 0
T3 484 1 0 0
T25 482 1 0 0
T26 482 1 0 0
T27 484 1 0 0
T28 481 1 0 0
T29 482 1 0 0
T30 484 1 0 0
T31 483 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 950 0 0
ReqTimeout_A 304535 951 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 950 0 0
T1 15502 1 0 0
T2 21080 1 0 0
T3 21301 1 0 0
T25 34171 1 0 0
T26 32501 1 0 0
T27 12772 1 0 0
T28 41123 1 0 0
T29 41624 1 0 0
T30 10312 1 0 0
T31 21039 1 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 951 0 0
T1 485 1 0 0
T2 483 1 0 0
T3 484 1 0 0
T25 482 1 0 0
T26 482 1 0 0
T27 484 1 0 0
T28 481 1 0 0
T29 482 1 0 0
T30 484 1 0 0
T31 483 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 933 0 0
ReqTimeout_A 304535 934 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 933 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 9 0 0
T19 94858 9 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 934 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 9 0 0
T19 778 9 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 900 0 0
ReqTimeout_A 304535 901 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 900 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 4 0 0
T19 94858 4 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 901 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 4 0 0
T19 778 4 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 914 0 0
ReqTimeout_A 304535 915 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 914 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 5 0 0
T20 980143 17 0 0
T21 404283 20 0 0
T22 457970 128 0 0
T23 101358 10 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 915 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 5 0 0
T20 8566 17 0 0
T21 8484 20 0 0
T22 9940 128 0 0
T23 4453 10 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 920 0 0
ReqTimeout_A 304535 921 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 920 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 1 0 0
T18 200740 6 0 0
T19 94858 4 0 0
T20 980143 18 0 0
T21 404283 19 0 0
T22 457970 126 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 921 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 1 0 0
T18 804 6 0 0
T19 778 4 0 0
T20 8566 18 0 0
T21 8484 19 0 0
T22 9940 126 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 893 0 0
ReqTimeout_A 304535 894 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 893 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 1 0 0
T19 94858 2 0 0
T20 980143 20 0 0
T21 404283 17 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 894 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 2 0 0
T20 8566 20 0 0
T21 8484 17 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 926 0 0
ReqTimeout_A 304535 928 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 926 0 0
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 13 0 0
T19 94858 4 0 0
T20 980143 19 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 928 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 13 0 0
T19 778 4 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T16

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 953 0 0
ReqTimeout_A 304535 954 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 953 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 19 0 0
T17 4768 2 0 0
T18 200740 8 0 0
T19 94858 5 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 128 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 954 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 19 0 0
T17 408 2 0 0
T18 804 8 0 0
T19 778 5 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 914 0 0
ReqTimeout_A 304535 915 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 914 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 6 0 0
T19 94858 2 0 0
T20 980143 18 0 0
T21 404283 20 0 0
T22 457970 126 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 915 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 6 0 0
T19 778 2 0 0
T20 8566 18 0 0
T21 8484 20 0 0
T22 9940 126 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T32,T13,T14
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 908 0 0
ReqTimeout_A 304535 909 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 908 0 0
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 1 0 0
T19 94858 7 0 0
T20 980143 19 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 909 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 7 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 916 0 0
ReqTimeout_A 304535 918 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 916 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 12 0 0
T19 94858 10 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 128 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 918 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 12 0 0
T19 778 10 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 128 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 929 0 0
ReqTimeout_A 304535 930 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 929 0 0
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 1 0 0
T19 94858 5 0 0
T20 980143 20 0 0
T21 404283 18 0 0
T22 457970 128 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 930 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 5 0 0
T20 8566 20 0 0
T21 8484 18 0 0
T22 9940 128 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 905 0 1
ReqTimeout_A 304535 907 0 1
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 905 0 1
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 1 0 0
T19 94858 4 0 0
T20 980143 19 0 0
T21 404283 19 0 0
T22 457970 128 0 0
T37 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 907 0 1
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 1 0 0
T19 778 4 0 0
T20 8566 19 0 0
T21 8484 19 0 0
T22 9940 128 0 0
T37 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 945 0 1
ReqTimeout_A 304535 946 0 1
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 945 0 1
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 3 0 0
T19 94858 2 0 0
T20 980143 19 0 0
T21 404283 20 0 0
T22 457970 128 0 0
T35 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 946 0 1
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 2 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 128 0 0
T35 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 928 0 1
ReqTimeout_A 304535 929 0 1
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 928 0 1
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 1 0 0
T18 200740 8 0 1
T19 94858 6 0 0
T20 980143 19 0 0
T21 404283 19 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 929 0 1
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 1 0 0
T18 804 8 0 1
T19 778 6 0 0
T20 8566 19 0 0
T21 8484 19 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 926 0 0
ReqTimeout_A 304535 927 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 926 0 0
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 5 0 0
T19 94858 6 0 0
T20 980143 19 0 0
T21 404283 20 0 0
T22 457970 127 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 927 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 5 0 0
T19 778 6 0 0
T20 8566 19 0 0
T21 8484 20 0 0
T22 9940 127 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 924 0 0
ReqTimeout_A 304535 925 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 924 0 0
T13 972617 10 0 0
T14 202909 9 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 3 0 0
T19 94858 2 0 0
T20 980143 20 0 0
T21 404283 19 0 0
T22 457970 128 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 925 0 0
T13 4451 10 0 0
T14 4457 9 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 3 0 0
T19 778 2 0 0
T20 8566 20 0 0
T21 8484 19 0 0
T22 9940 128 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T16
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 304535 53953 0 0
HungHandShake_A 60874341 917 0 0
ReqTimeout_A 304535 918 0 0
SrcBusyKnown_A 60874341 60773484 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 53953 0 0
T1 485 85 0 0
T2 483 83 0 0
T3 484 84 0 0
T4 444 44 0 0
T7 422 22 0 0
T8 429 29 0 0
T9 422 22 0 0
T10 422 22 0 0
T11 422 22 0 0
T12 424 24 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 917 0 0
T13 972617 10 0 0
T14 202909 10 0 0
T15 2936 2 0 0
T16 242774 20 0 0
T17 4768 2 0 0
T18 200740 2 0 0
T19 94858 7 0 0
T20 980143 20 0 0
T21 404283 20 0 0
T22 457970 126 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 304535 918 0 0
T13 4451 10 0 0
T14 4457 10 0 0
T15 422 2 0 0
T16 8491 20 0 0
T17 408 2 0 0
T18 804 2 0 0
T19 778 7 0 0
T20 8566 20 0 0
T21 8484 20 0 0
T22 9940 126 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 60874341 60773484 0 0
T1 15502 15438 0 0
T2 21080 20988 0 0
T3 21301 21244 0 0
T4 10893 10797 0 0
T7 11411 11325 0 0
T8 3866 3816 0 0
T9 11592 11495 0 0
T10 11752 11691 0 0
T11 11773 11674 0 0
T12 4919 4859 0 0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT32,T13,T14

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT13,T14,T16
10CoveredT32,T13,T14
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT32,T13,T14
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T32,T13,T14
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2</