53b9e7d8e| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | TOTAL | 155 | 205 | 75.61 | |
| V2 | combo_detect | sysrst_ctrl_combo_detect | 0 | 0 | -- |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 0 | 0 | -- |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 0 | 0 | -- |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_override_test | 0 | 0 | -- |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 0 | 0 | -- |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 0 | 0 | -- |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 0 | 0 | -- |
| V2 | alert_test | sysrst_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 50 | 0.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 140 | 190 | 73.68 | |
| V2S | tl_intg_err | sysrst_ctrl_tl_intg_err | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| Unmapped tests | sysrst_ctrl_stress_all | 0 | 50 | 0.00 | |
| TOTAL | 315 | 515 | 61.17 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 12 | 5 | 4 | 33.33 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.73 | 99.57 | 82.92 | 98.48 | -- | 92.79 | 91.55 | 79.06 |
UVM_WARNING [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.sysrst_ctrl_stress_all.1842114246
Line 298, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.sysrst_ctrl_stress_all.3446484623
Line 298, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.sysrst_ctrl_stress_all_with_rand_reset.59543426
Line 299, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 8046784 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 8046784 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.sysrst_ctrl_stress_all_with_rand_reset.4013017138
Line 299, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 8039586 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 8039586 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (sysrst_ctrl_scoreboard.sv:95) scoreboard [scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_* has 50 failures:
0.sysrst_ctrl_combo_detect_ec_rst.3093785418
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/out/run.log
UVM_ERROR @ 8076718 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_ERROR @ 8086718 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_INFO @ 8086718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sysrst_ctrl_combo_detect_ec_rst.3038159258
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/out/run.log
UVM_ERROR @ 8075439 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_ERROR @ 8085439 ps: (sysrst_ctrl_scoreboard.sv:95) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: sysrst_ctrl_reg_block.com_sel_ctl_0
UVM_INFO @ 8085439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:460) [sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (* [*] vs *xX [x]) has 50 failures:
0.sysrst_ctrl_intr_test.4043813132
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/out/run.log
UVM_ERROR @ 8347322 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8367524 ps: (cip_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 2/3
UVM_ERROR @ 8640251 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8640251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sysrst_ctrl_intr_test.2250275856
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/out/run.log
UVM_ERROR @ 8386219 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8386219 ps: (cip_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 2/3
UVM_ERROR @ 8649379 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8649379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.