---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.sysrst_ctrl_csr_assert.intr_enable_rd_A	0	0	2102060	0	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_out_ctl_rd_A	0	0	2102060	0	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_out_value_rd_A	0	0	2102060	0	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_ctl_rd_A	0	0	2102060	0	0	0
tb.dut.u_reg.u_aon_tgl.SyncReqAckHoldReq	0	0	302039	0	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0
tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync.SyncReqAckHoldReq	0	0	58163845	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	2102060	2090820	0	0
tb.dut.BatOEnKnown	0	0	2102060	2090820	0	0
tb.dut.BatOKnown	0	0	2102060	2090820	0	0
tb.dut.ECRSTOEnKnown	0	0	2102060	2090820	0	0
tb.dut.ECRSTOKnown	0	0	2102060	2090820	0	0
tb.dut.FlashWpOEnKnown	0	0	2102060	2090820	0	0
tb.dut.FlashWpOKnown	0	0	2102060	2090820	0	0
tb.dut.IntrSysRstCtrlOKnown	0	0	2102060	2090820	0	0
tb.dut.Key0OEnKnown	0	0	2102060	2090820	0	0
tb.dut.Key0OKnown	0	0	2102060	2090820	0	0
tb.dut.Key1OEnKnown	0	0	2102060	2090820	0	0
tb.dut.Key1OKnown	0	0	2102060	2090820	0	0
tb.dut.Key2OEnKnown	0	0	2102060	2090820	0	0
tb.dut.Key2OKnown	0	0	2102060	2090820	0	0
tb.dut.OTRstOKnown	0	0	2102060	2090820	0	0
tb.dut.OTWkOKnown	0	0	2102060	2090820	0	0
tb.dut.PwrbOEnKnown	0	0	2102060	2090820	0	0
tb.dut.PwrbOKnown	0	0	2102060	2090820	0	0
tb.dut.TlOAReadyKnown	0	0	2102060	2090820	0	0
tb.dut.TlODValidKnown	0	0	2102060	2090820	0	0
tb.dut.Z3WakeupOEnKnown	0	0	2102060	2090820	0	0
tb.dut.Z3WwakupOKnown	0	0	2102060	2090820	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2102060	713817	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2102060	2090820	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2102060	2090820	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2102060	7520	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2102060	2090820	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2102060	2090820	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
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tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	150	150	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2102162	1100	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAligned_M	0	0	2102162	713817	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2102162	713284	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2102162	5203	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcode_M	0	0	2102162	713817	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2102162	713817	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2102162	7520	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2102162	713817	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2102162	7520	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2102162	7520	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2102162	7520	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMask_M	0	0	2102162	713817	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMask_M	0	0	2102162	713817	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	150	150	0	0
tb.dut.u_reg.en2addrHit	0	0	58163845	77260	0	0
tb.dut.u_reg.reAfterRv	0	0	58163845	77260	0	0
tb.dut.u_reg.rePulse	0	0	58163845	46846	0	0
tb.dut.u_reg.u_aon_tgl.SyncReqAckAckNeedsReq	0	0	58163845	13026	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.HungHandShake_A	0	0	58163845	842	0	1
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.ReqTimeout_A	0	0	302039	843	0	1
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	843	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.HungHandShake_A	0	0	58163845	844	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.ReqTimeout_A	0	0	302039	845	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	845	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	315	315	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.HungHandShake_A	0	0	58163845	829	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.ReqTimeout_A	0	0	302039	830	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
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tb.dut.u_reg.u_com_det_ctl_1_cdc.ReqTimeout_A	0	0	302039	844	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	844	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.HungHandShake_A	0	0	58163845	839	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.ReqTimeout_A	0	0	302039	840	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	840	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.HungHandShake_A	0	0	58163845	845	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.ReqTimeout_A	0	0	302039	846	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	846	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.HungHandShake_A	0	0	58163845	849	0	1
tb.dut.u_reg.u_com_out_ctl_0_cdc.ReqTimeout_A	0	0	302039	850	0	1
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	850	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.HungHandShake_A	0	0	58163845	851	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.ReqTimeout_A	0	0	302039	852	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	852	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.HungHandShake_A	0	0	58163845	864	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.ReqTimeout_A	0	0	302039	865	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	865	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.HungHandShake_A	0	0	58163845	828	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.ReqTimeout_A	0	0	302039	828	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	828	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.HungHandShake_A	0	0	58163845	864	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.ReqTimeout_A	0	0	302039	865	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	865	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.HungHandShake_A	0	0	58163845	856	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.ReqTimeout_A	0	0	302039	857	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	857	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.HungHandShake_A	0	0	58163845	878	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.ReqTimeout_A	0	0	302039	879	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	879	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.HungHandShake_A	0	0	58163845	866	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.ReqTimeout_A	0	0	302039	867	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	867	0	0
tb.dut.u_reg.u_combo_intr_status_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_combo_intr_status_cdc.HungHandShake_A	0	0	58163845	487	0	1
tb.dut.u_reg.u_combo_intr_status_cdc.ReqTimeout_A	0	0	302039	488	0	1
tb.dut.u_reg.u_combo_intr_status_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	488	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.HungHandShake_A	0	0	58163845	872	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.ReqTimeout_A	0	0	302039	873	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	873	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.HungHandShake_A	0	0	58163845	875	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.ReqTimeout_A	0	0	302039	876	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	876	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.HungHandShake_A	0	0	58163845	858	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.ReqTimeout_A	0	0	302039	859	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	859	0	0
tb.dut.u_reg.u_key_intr_status_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_key_intr_status_cdc.HungHandShake_A	0	0	58163845	497	0	3
tb.dut.u_reg.u_key_intr_status_cdc.ReqTimeout_A	0	0	302039	498	0	3
tb.dut.u_reg.u_key_intr_status_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	498	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.HungHandShake_A	0	0	58163845	1858	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.ReqTimeout_A	0	0	302039	1859	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	1859	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.HungHandShake_A	0	0	58163845	920	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.ReqTimeout_A	0	0	302039	921	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	921	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.HungHandShake_A	0	0	58163845	897	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.ReqTimeout_A	0	0	302039	898	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	898	0	0
tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_pin_out_value_cdc.HungHandShake_A	0	0	58163845	863	0	1
tb.dut.u_reg.u_pin_out_value_cdc.ReqTimeout_A	0	0	302039	863	0	1
tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	863	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	315	315	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	315	315	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	315	315	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	315	315	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.HungHandShake_A	0	0	58163845	848	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.ReqTimeout_A	0	0	302039	848	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	848	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.HungHandShake_A	0	0	58163845	870	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.ReqTimeout_A	0	0	302039	871	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	871	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.HungHandShake_A	0	0	58163845	895	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.ReqTimeout_A	0	0	302039	896	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	896	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.HungHandShake_A	0	0	58163845	855	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.ReqTimeout_A	0	0	302039	856	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	856	0	0
tb.dut.u_reg.u_ulp_status_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_ulp_status_cdc.HungHandShake_A	0	0	58163845	506	0	0
tb.dut.u_reg.u_ulp_status_cdc.ReqTimeout_A	0	0	302039	506	0	0
tb.dut.u_reg.u_ulp_status_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	506	0	0
tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A	0	0	302039	49849	0	0
tb.dut.u_reg.u_wkup_status_cdc.HungHandShake_A	0	0	58163845	484	0	1
tb.dut.u_reg.u_wkup_status_cdc.ReqTimeout_A	0	0	302039	485	0	1
tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A	0	0	58163845	58051189	0	0
tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync.SyncReqAckAckNeedsReq	0	0	302039	485	0	0
tb.dut.u_reg.wePulse	0	0	58163845	30414	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.HungHandShake_A	0	0	58163845	842	0	1
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.ReqTimeout_A	0	0	302039	843	0	1
tb.dut.u_reg.u_com_out_ctl_0_cdc.HungHandShake_A	0	0	58163845	849	0	1
tb.dut.u_reg.u_com_out_ctl_0_cdc.ReqTimeout_A	0	0	302039	850	0	1
tb.dut.u_reg.u_combo_intr_status_cdc.HungHandShake_A	0	0	58163845	487	0	1
tb.dut.u_reg.u_combo_intr_status_cdc.ReqTimeout_A	0	0	302039	488	0	1
tb.dut.u_reg.u_key_intr_status_cdc.HungHandShake_A	0	0	58163845	497	0	3
tb.dut.u_reg.u_key_intr_status_cdc.ReqTimeout_A	0	0	302039	498	0	3
tb.dut.u_reg.u_pin_out_value_cdc.HungHandShake_A	0	0	58163845	863	0	1
tb.dut.u_reg.u_pin_out_value_cdc.ReqTimeout_A	0	0	302039	863	0	1
tb.dut.u_reg.u_wkup_status_cdc.HungHandShake_A	0	0	58163845	484	0	1
tb.dut.u_reg.u_wkup_status_cdc.ReqTimeout_A	0	0	302039	485	0	1

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2102162	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2102162	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2102162	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2102162	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2102162	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2102162	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2102162	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2102162	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2102162	41323	41323	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2102162	1863	1863	150

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2102162	41323	41323	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2102162	1863	1863	150