Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 93.29 98.93 86.68 97.97 91.30 91.55
dut 93.29 98.93 86.68 97.97 91.30 91.55
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 53.41 68.75 100.00 44.90 0.00
tlul_assert_device 99.07 100.00 100.00 97.20
u_prim_edge_detector 100.00 100.00 100.00
g_sync.u_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_intr_hw 100.00 100.00 100.00
u_reg 93.93 99.57 95.70 96.67 83.78
subtree...
u_sysrst_ctrl_autoblock 72.30 97.06 55.56 64.29
u_sysrst_ctrl_detect 74.39 96.67 58.33 68.18
u_prim_filter_ctr 82.62 92.86 80.00 75.00
u_sysrst_ctrl_combo 73.85 98.62 56.25 66.67
gen_combo_trigger[0].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[0].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64
u_prim_filter_ctr 75.56 100.00 60.00 66.67
gen_combo_trigger[1].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[1].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64
u_prim_filter_ctr 75.56 100.00 60.00 66.67
gen_combo_trigger[2].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[2].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64
u_prim_filter_ctr 75.56 100.00 60.00 66.67
gen_combo_trigger[3].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[3].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64
u_prim_filter_ctr 75.56 100.00 60.00 66.67
u_sysrst_ctrl_keyintr 72.93 96.77 53.85 68.18
gen_keyfsm[0].u_sysrst_ctrl_detect 72.90 96.67 53.85 68.18
u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_keyfsm[1].u_sysrst_ctrl_detect 72.90 96.67 53.85 68.18
u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_keyfsm[2].u_sysrst_ctrl_detect 72.90 96.67 53.85 68.18
u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_keyfsm[3].u_sysrst_ctrl_detect 72.90 96.67 53.85 68.18
u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_keyfsm[4].u_sysrst_ctrl_detect 72.90 96.67 53.85 68.18
u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_keyfsm[5].u_sysrst_ctrl_detect 72.90 96.67 53.85 68.18
u_prim_filter_ctr 82.62 92.86 80.00 75.00
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_cfg_ac_present_i_pin 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_ulp 81.81 96.30 75.00 74.14
u_sysrst_ctrl_detect_ac_present 81.02 95.83 75.00 72.22
u_prim_filter_ctr 82.62 92.86 80.00 75.00
u_sysrst_ctrl_detect_lid_open 82.10 96.30 75.00 75.00
u_prim_filter_ctr 82.62 92.86 80.00 75.00
u_sysrst_ctrl_detect_pwrb 82.10 96.30 75.00 75.00
u_prim_filter_ctr 82.62 92.86 80.00 75.00
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