Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_filter_ctr
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.22 100.00 70.00 91.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr 75.56 100.00 60.00 66.67
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr 75.56 100.00 60.00 66.67
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr 75.56 100.00 60.00 66.67
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr 75.56 100.00 60.00 66.67
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect.u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_prim_filter_ctr 82.62 92.86 80.00 75.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_prim_filter_ctr 82.62 92.86 80.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.62 100.00 42.86 60.00 gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.62 100.00 42.86 60.00 gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.62 100.00 42.86 60.00 gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.56 100.00 60.00 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.62 100.00 42.86 60.00 gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.62 100.00 42.86 60.00 u_sysrst_ctrl_detect


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.56 100.00 66.67 75.00 u_sysrst_ctrl_detect_pwrb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.56 100.00 66.67 75.00 u_sysrst_ctrl_detect_lid_open


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.78 100.00 66.67 66.67 u_sysrst_ctrl_detect_ac_present


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.83 100.00 37.50 60.00 gen_keyfsm[0].u_sysrst_ctrl_detect


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.83 100.00 37.50 60.00 gen_keyfsm[1].u_sysrst_ctrl_detect


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.83 100.00 37.50 60.00 gen_keyfsm[2].u_sysrst_ctrl_detect


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.83 100.00 37.50 60.00 gen_keyfsm[3].u_sysrst_ctrl_detect


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.83 100.00 37.50 60.00 gen_keyfsm[4].u_sysrst_ctrl_detect


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect.u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.83 100.00 37.50 60.00 gen_keyfsm[5].u_sysrst_ctrl_detect


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_prim_filter_ctr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.62 92.86 80.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 1 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Module : prim_filter_ctr ( parameter AsyncOn=0,CntWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect.u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_prim_filter_ctr

SCORECOND
82.62 80.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_prim_filter_ctr

TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Cond Coverage for Module : prim_filter_ctr ( parameter AsyncOn=0,CntWidth=32 )
Cond Coverage for Module self-instances :
SCORECOND
75.56 60.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

SCORECOND
75.56 60.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

SCORECOND
75.56 60.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

SCORECOND
75.56 60.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr

TotalCoveredPercent
Conditions5360.00
Logical5360.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T2

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Module : prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 11 91.67
TERNARY 75 3 3 100.00
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 3 100.00
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 1 1
==> MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
TotalCoveredPercent
Conditions5360.00
Logical5360.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T2

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 8 66.67
TERNARY 75 3 1 33.33
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 1 1
==> MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
TotalCoveredPercent
Conditions5360.00
Logical5360.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T2

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 8 66.67
TERNARY 75 3 1 33.33
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 1 1
==> MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
TotalCoveredPercent
Conditions5360.00
Logical5360.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T2

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 8 66.67
TERNARY 75 3 1 33.33
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS5844100.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 1 1
==> MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
TotalCoveredPercent
Conditions5360.00
Logical5360.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T2

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 8 66.67
TERNARY 75 3 1 33.33
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT12,T24,T26

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T12,T24,T26
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT2,T12,T23

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T12,T23
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT2,T12,T23

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T12,T23
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect.u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect.u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_prim_filter_ctr
Line No.TotalCoveredPercent
TOTAL141392.86
CONT_ASSIGN4611100.00
ALWAYS5033100.00
ALWAYS584375.00
ALWAYS6633100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
50 1 1
51 1 1
53 1 1
58 1 1
59 1 1
60 1 1
61 0 1
MISSING_ELSE
66 1 1
67 1 1
69 1 1
74 1 1
75 1 1
79 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_prim_filter_ctr
TotalCoveredPercent
Conditions5480.00
Logical5480.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_prim_filter_ctr
Line No.TotalCoveredPercent
Branches 12 9 75.00
TERNARY 75 3 2 66.67
TERNARY 79 2 1 50.00
IF 50 2 2 100.00
IF 58 3 2 66.67
IF 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 ((filter_synced != filter_q)) ? -2-: 75 ((diff_ctr_q >= thresh_i)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 79 (enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Not Covered


LineNo. Expression -1-: 50 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Not Covered
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 66 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%