Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_ulp_status_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_wkup_status_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_cdc 98.33 100.00 93.33 100.00 100.00
tb.dut.u_reg.u_key_intr_status_cdc 98.33 100.00 93.33 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00



Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.70 100.00 93.33 94.12 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync 80.30 100.00 90.91 50.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 9297806 1659351 0 0
HungHandShake_A 1607230634 27954 0 5
ReqTimeout_A 9297806 27954 0 5
SrcBusyKnown_A 1607230634 1603840592 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9297806 1659351 0 0
T1 13978 2378 0 0
T2 14094 2494 0 0
T3 14007 2407 0 0
T4 11745 145 0 0
T5 14558 2958 0 0
T6 14587 2987 0 0
T8 12354 754 0 0
T9 12963 1363 0 0
T10 11687 87 0 0
T11 12238 638 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1607230634 27954 0 5
T1 83694 21 0 0
T2 22014 21 0 0
T3 58054 21 0 0
T5 50762 20 0 0
T12 56642 21 0 0
T13 5468257 201 0 0
T14 97584 35 0 0
T15 89547 38 0 0
T16 45904 19 0 0
T17 1725181 98 0 0
T18 87191 35 0 0
T19 1923655 190 0 0
T20 416176 38 0 0
T21 3332068 262 0 0
T22 61047 38 0 0
T23 41902 21 0 0
T24 80900 21 0 0
T25 41854 20 0 0
T26 15978 20 0 0
T27 40830 20 0 0
T28 10409 20 0 0
T52 0 0 0 1
T53 0 0 0 1
T54 0 0 0 1
T55 0 0 0 1
T56 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9297806 27954 0 5
T1 964 21 0 0
T2 972 21 0 0
T3 966 21 0 0
T5 502 20 0 0
T12 964 21 0 0
T13 29450 201 0 0
T14 7771 35 0 0
T15 7752 38 0 0
T16 7752 19 0 0
T17 14611 98 0 0
T18 7752 35 0 0
T19 84512 190 0 0
T20 8949 38 0 0
T21 26619 262 0 0
T22 7809 38 0 0
T23 964 21 0 0
T24 964 21 0 0
T25 482 20 0 0
T26 485 20 0 0
T27 482 20 0 0
T28 485 20 0 0
T52 0 0 0 1
T53 0 0 0 1
T54 0 0 0 1
T55 0 0 0 1
T56 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1607230634 1603840592 0 0
T1 1213563 1210837 0 0
T2 319203 317550 0 0
T3 841783 839463 0 0
T4 72993 70412 0 0
T5 1472098 1469807 0 0
T6 681761 679064 0 0
T8 96744 94743 0 0
T9 182178 179307 0 0
T10 59508 57391 0 0
T11 340402 337908 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 852 0 1
ReqTimeout_A 320614 852 0 1
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 852 0 1
T13 287803 5 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 3 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 20 0 0
T22 3213 2 0 0
T53 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 852 0 1
T13 1550 5 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 20 0 0
T22 411 2 0 0
T53 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 876 0 1
ReqTimeout_A 320614 876 0 1
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 876 0 1
T13 287803 10 0 0
T14 5136 1 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 9 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 20 0 0
T22 3213 2 0 0
T54 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 876 0 1
T13 1550 10 0 0
T14 409 1 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 9 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 20 0 0
T22 411 2 0 0
T54 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 869 0 0
ReqTimeout_A 320614 869 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 869 0 0
T13 287803 4 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 7 0 0
T18 4589 1 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 4 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 869 0 0
T13 1550 4 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 7 0 0
T18 408 1 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 4 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 865 0 0
ReqTimeout_A 320614 865 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 865 0 0
T13 287803 12 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 2 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 11 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 865 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 11 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 859 0 0
ReqTimeout_A 320614 859 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 859 0 0
T13 287803 7 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 1 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 5 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 859 0 0
T13 1550 7 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 1 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 5 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 478 0 0
ReqTimeout_A 320614 478 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 478 0 0
T13 287803 13 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 3 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 17 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 478 0 0
T13 1550 13 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 17 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 496 0 0
ReqTimeout_A 320614 496 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 496 0 0
T13 287803 8 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 2 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 12 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 496 0 0
T13 1550 8 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 12 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 1895 0 0
ReqTimeout_A 320614 1895 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 1895 0 0
T1 41847 20 0 0
T2 11007 20 0 0
T3 29027 20 0 0
T12 28321 20 0 0
T23 20951 20 0 0
T24 40450 20 0 0
T25 41854 20 0 0
T26 15978 20 0 0
T27 40830 20 0 0
T28 10409 20 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1895 0 0
T1 482 20 0 0
T2 486 20 0 0
T3 483 20 0 0
T12 482 20 0 0
T23 482 20 0 0
T24 482 20 0 0
T25 482 20 0 0
T26 485 20 0 0
T27 482 20 0 0
T28 485 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 1909 0 1
ReqTimeout_A 320614 1909 0 1
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 1909 0 1
T1 41847 1 0 0
T2 11007 1 0 0
T3 29027 1 0 0
T5 50762 20 0 0
T6 23509 20 0 0
T7 12672 20 0 0
T12 28321 1 0 0
T23 20951 1 0 0
T24 40450 1 0 0
T29 25572 20 0 0
T55 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1909 0 1
T1 482 1 0 0
T2 486 1 0 0
T3 483 1 0 0
T5 502 20 0 0
T6 503 20 0 0
T7 504 20 0 0
T12 482 1 0 0
T23 482 1 0 0
T24 482 1 0 0
T29 503 20 0 0
T55 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 1921 0 0
ReqTimeout_A 320614 1921 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 1921 0 0
T1 41847 1 0 0
T2 11007 1 0 0
T3 29027 1 0 0
T5 50762 20 0 0
T6 23509 20 0 0
T7 12672 20 0 0
T12 28321 1 0 0
T23 20951 1 0 0
T24 40450 1 0 0
T29 25572 20 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1921 0 0
T1 482 1 0 0
T2 486 1 0 0
T3 483 1 0 0
T5 502 20 0 0
T6 503 20 0 0
T7 504 20 0 0
T12 482 1 0 0
T23 482 1 0 0
T24 482 1 0 0
T29 503 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT5,T6,T7

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT5,T6,T7

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT5,T6,T7
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T5,T6,T7
0 0 1 Covered T5,T6,T7
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T5,T6,T7
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T5,T6,T7
0 0 1 Covered T5,T6,T7
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 1875 0 0
ReqTimeout_A 320614 1875 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 1875 0 0
T5 50762 20 0 0
T6 23509 20 0 0
T7 12672 20 0 0
T29 25572 20 0 0
T30 24928 20 0 0
T31 49720 20 0 0
T32 50300 20 0 0
T33 12990 20 0 0
T34 51766 20 0 0
T35 13372 20 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1875 0 0
T5 502 20 0 0
T6 503 20 0 0
T7 504 20 0 0
T29 503 20 0 0
T30 502 20 0 0
T31 502 20 0 0
T32 502 20 0 0
T33 507 20 0 0
T34 502 20 0 0
T35 505 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 864 0 0
ReqTimeout_A 320614 864 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 864 0 0
T13 287803 7 0 0
T14 5136 1 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 5 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 20 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 864 0 0
T13 1550 7 0 0
T14 409 1 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 20 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 892 0 0
ReqTimeout_A 320614 892 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 892 0 0
T13 287803 18 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 6 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 14 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 892 0 0
T13 1550 18 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 6 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 14 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 871 0 0
ReqTimeout_A 320614 871 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 871 0 0
T13 287803 6 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 8 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 15 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 871 0 0
T13 1550 6 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 8 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 15 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 881 0 0
ReqTimeout_A 320614 881 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 881 0 0
T13 287803 12 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 1 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 10 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 881 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 1 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 10 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 902 0 0
ReqTimeout_A 320614 902 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 902 0 0
T13 287803 12 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 11 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 12 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 902 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 11 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 12 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 883 0 0
ReqTimeout_A 320614 883 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 883 0 0
T13 287803 13 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 2 0 0
T18 4589 1 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 16 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 883 0 0
T13 1550 13 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 1 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 16 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 885 0 0
ReqTimeout_A 320614 885 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 885 0 0
T13 287803 11 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 10 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 21 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 885 0 0
T13 1550 11 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 10 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 21 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 853 0 0
ReqTimeout_A 320614 853 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 853 0 0
T13 287803 14 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 2 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 17 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 853 0 0
T13 1550 14 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 17 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 860 0 0
ReqTimeout_A 320614 860 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 860 0 0
T13 287803 13 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 6 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 10 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 860 0 0
T13 1550 13 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 6 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 10 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 855 0 0
ReqTimeout_A 320614 855 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 855 0 0
T13 287803 10 0 0
T14 5136 1 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 6 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 6 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 855 0 0
T13 1550 10 0 0
T14 409 1 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 6 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 6 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 888 0 0
ReqTimeout_A 320614 888 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 888 0 0
T13 287803 12 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 5 0 0
T18 4589 1 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 11 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 888 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 1 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 11 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 864 0 1
ReqTimeout_A 320614 864 0 1
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 864 0 1
T13 287803 14 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 3 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 9 0 0
T22 3213 2 0 0
T52 0 0 0 1

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 864 0 1
T13 1550 14 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 9 0 0
T22 411 2 0 0
T52 0 0 0 1

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 872 0 0
ReqTimeout_A 320614 872 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 872 0 0
T13 287803 17 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 3 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 18 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 872 0 0
T13 1550 17 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 18 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 883 0 0
ReqTimeout_A 320614 883 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 883 0 0
T13 287803 7 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 5 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 16 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 883 0 0
T13 1550 7 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 16 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 879 0 0
ReqTimeout_A 320614 879 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 879 0 0
T13 287803 6 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 5 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 12 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 879 0 0
T13 1550 6 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 12 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 143 if ((!rst_src_ni)) -2-: 145 if (src_req) -3-: 147 if (dst_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstReqKnown_A 320614 57219 0 0
HungHandShake_A 55421746 917 0 0
ReqTimeout_A 320614 917 0 0
SrcBusyKnown_A 55421746 55304848 0 0


DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 57219 0 0
T1 482 82 0 0
T2 486 86 0 0
T3 483 83 0 0
T4 405 5 0 0
T5 502 102 0 0
T6 503 103 0 0
T8 426 26 0 0
T9 447 47 0 0
T10 403 3 0 0
T11 422 22 0 0

HungHandShake_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 917 0 0
T13 287803 8 0 0
T14 5136 2 0 0
T15 4713 2 0 0
T16 2416 1 0 0
T17 90799 5 0 0
T18 4589 2 0 0
T19 101245 10 0 0
T20 21904 2 0 0
T21 175372 10 0 0
T22 3213 2 0 0

ReqTimeout_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 917 0 0
T13 1550 8 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 10 0 0
T22 411 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 55304848 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4411100.00
ALWAYS5066100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN7911100.00
ALWAYS8299100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN13211100.00
ALWAYS14366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
MISSING_ELSE
59 1 1
79 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
97 1 1
98 1 1
MISSING_ELSE
104 1 1
109 1 1
110 1 1
132 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_busy_q && src_ack)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       85
 EXPRESSION (src_req && ((!busy)))
             ---1---    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT13,T14,T15

 LINE       88
 EXPRESSION ((src_busy_q && src_ack) || (src_update_i && ((!busy))))
             -----------1-----------    -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01CoveredT19,T37,T51
10CoveredT13,T14,T15
11CoveredT13,T14,T15

 LINE       88
 SUB-EXPRESSION (src_update_i && ((!busy)))
                 ------1-----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT13,T14,T15
11CoveredT1,T4,T2

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
Line No.TotalCoveredPercent
Branches 12 12 100.00
IF 50 4 4 100.00
IF 82 4 4 100.00
IF 143 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 if ((!rst_src_ni)) -2-: 52 if (src_req) -3-: 54 if ((src_busy_q && src_ack))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T13,T14,T15
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 82 if ((!rst_src_ni)) -2-: 85 if ((src_req && (!busy))) -3-: 88 if (((src_busy_q && src_ack) || (src_update_i && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T13,T14,T15
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T4,