Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_combo
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_combo 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_combo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.85 98.62 56.25 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.72 100.00 25.00 97.86 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_combo_trigger[0].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[0].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64
gen_combo_trigger[1].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[1].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64
gen_combo_trigger[2].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[2].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64
gen_combo_trigger[3].u_combo_act 71.94 100.00 53.33 62.50
gen_combo_trigger[3].u_prim_filter_ctr 82.62 92.86 80.00 75.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_debounce 71.21 100.00 50.00 63.64


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_combo
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
53 4 4
63 4 4
67 4 4
123 1 1
126 1 1
127 1 1
130 1 1
135 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%