Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_pin_in_value_ac_present 90.00 100.00 80.00
tb.dut.u_reg.u_pin_in_value_ec_rst_l 90.00 100.00 80.00
tb.dut.u_reg.u_pin_in_value_pwrb_in 90.00 100.00 80.00
tb.dut.u_reg.u_pin_in_value_key0_in 90.00 100.00 80.00
tb.dut.u_reg.u_pin_in_value_key1_in 90.00 100.00 80.00
tb.dut.u_reg.u_pin_in_value_key2_in 90.00 100.00 80.00
tb.dut.u_reg.u_pin_in_value_lid_open 90.00 100.00 80.00
tb.dut.u_reg.u_intr_state 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable 100.00 100.00 100.00
tb.dut.u_reg.u_regwen 100.00 100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_status 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_status 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_in 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_out 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_in 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_out 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_in 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_out 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_in 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_out 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_ac_present 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_bat_disable 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_lid_open 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_bat_disable 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_pwrb_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key0_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key1_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key2_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_bat_disable 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_ec_rst_l 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_pwrb_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_key0_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_key1_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_key2_out 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_z3_wakeup 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_flash_wp_l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3 100.00 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo0_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo1_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo2_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo3_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_pwrb_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key0_in_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key1_in_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key2_in_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ac_present_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_pwrb_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key0_in_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key1_in_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key2_in_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ac_present_l2h 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%