dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg.u_intr_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_intr_enable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_ec_rst_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_wkup_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_bat_disable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_key0_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_key1_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_key2_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_in_value_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 0.00 0.00
wr_en_data_arb 66.67 66.67


Module Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 0.00 0.00
wr_en_data_arb 66.67 66.67


Module Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 0.00 0.00
wr_en_data_arb 66.67 66.67


Module Instance : tb.dut.u_reg.u_pin_in_value_key0_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 0.00 0.00
wr_en_data_arb 66.67 66.67


Module Instance : tb.dut.u_reg.u_pin_in_value_key1_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 0.00 0.00
wr_en_data_arb 66.67 66.67


Module Instance : tb.dut.u_reg.u_pin_in_value_key2_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 0.00 0.00
wr_en_data_arb 66.67 66.67


Module Instance : tb.dut.u_reg.u_pin_in_value_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 0.00 0.00
wr_en_data_arb 66.67 66.67


Module Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_intr_state
tb.dut.u_reg.u_intr_enable
tb.dut.u_reg.u_regwen
tb.dut.u_reg.u_ec_rst_ctl
tb.dut.u_reg.u_ulp_ac_debounce_ctl
tb.dut.u_reg.u_ulp_lid_debounce_ctl
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
tb.dut.u_reg.u_ulp_ctl
tb.dut.u_reg.u_ulp_status
tb.dut.u_reg.u_wkup_status
tb.dut.u_reg.u_key_invert_ctl_key0_in
tb.dut.u_reg.u_key_invert_ctl_key0_out
tb.dut.u_reg.u_key_invert_ctl_key1_in
tb.dut.u_reg.u_key_invert_ctl_key1_out
tb.dut.u_reg.u_key_invert_ctl_key2_in
tb.dut.u_reg.u_key_invert_ctl_key2_out
tb.dut.u_reg.u_key_invert_ctl_pwrb_in
tb.dut.u_reg.u_key_invert_ctl_pwrb_out
tb.dut.u_reg.u_key_invert_ctl_ac_present
tb.dut.u_reg.u_key_invert_ctl_bat_disable
tb.dut.u_reg.u_key_invert_ctl_lid_open
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
tb.dut.u_reg.u_pin_out_ctl_bat_disable
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
tb.dut.u_reg.u_pin_out_ctl_pwrb_out
tb.dut.u_reg.u_pin_out_ctl_key0_out
tb.dut.u_reg.u_pin_out_ctl_key1_out
tb.dut.u_reg.u_pin_out_ctl_key2_out
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
tb.dut.u_reg.u_pin_out_value_bat_disable
tb.dut.u_reg.u_pin_out_value_ec_rst_l
tb.dut.u_reg.u_pin_out_value_pwrb_out
tb.dut.u_reg.u_pin_out_value_key0_out
tb.dut.u_reg.u_pin_out_value_key1_out
tb.dut.u_reg.u_pin_out_value_key2_out
tb.dut.u_reg.u_pin_out_value_z3_wakeup
tb.dut.u_reg.u_pin_out_value_flash_wp_l
tb.dut.u_reg.u_pin_in_value_ac_present
tb.dut.u_reg.u_pin_in_value_ec_rst_l
tb.dut.u_reg.u_pin_in_value_pwrb_in
tb.dut.u_reg.u_pin_in_value_key0_in
tb.dut.u_reg.u_pin_in_value_key1_in
tb.dut.u_reg.u_pin_in_value_key2_in
tb.dut.u_reg.u_pin_in_value_lid_open
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
tb.dut.u_reg.u_key_intr_debounce_ctl
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3
tb.dut.u_reg.u_com_det_ctl_0
tb.dut.u_reg.u_com_det_ctl_1
tb.dut.u_reg.u_com_det_ctl_2
tb.dut.u_reg.u_com_det_ctl_3
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2
Line Coverage for Instance : tb.dut.u_reg.u_intr_state
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_intr_state
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T36,T60,T44
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_regwen
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_regwen
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T20
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T5,T6,T7
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 49 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 49 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 49 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 49 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 49 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 49 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 49 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T1,T4,T2
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T19,T22
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T16,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T17,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T16,T17
0 0 Covered T1,T4,T2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%