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Module Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3
tb.dut.u_reg.u_combo_intr_status_combo0_h2l
tb.dut.u_reg.u_combo_intr_status_combo1_h2l
tb.dut.u_reg.u_combo_intr_status_combo2_h2l
tb.dut.u_reg.u_combo_intr_status_combo3_h2l
tb.dut.u_reg.u_key_intr_status_pwrb_h2l
tb.dut.u_reg.u_key_intr_status_key0_in_h2l
tb.dut.u_reg.u_key_intr_status_key1_in_h2l
tb.dut.u_reg.u_key_intr_status_key2_in_h2l
tb.dut.u_reg.u_key_intr_status_ac_present_h2l
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l
tb.dut.u_reg.u_key_intr_status_pwrb_l2h
tb.dut.u_reg.u_key_intr_status_key0_in_l2h
tb.dut.u_reg.u_key_intr_status_key1_in_l2h
tb.dut.u_reg.u_key_intr_status_key2_in_l2h
tb.dut.u_reg.u_key_intr_status_ac_present_l2h
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T16,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T16,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T16,T17
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T19
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T13,T14,T15
0 0 Covered T1,T4,T2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%