Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_pin_in_value_ac_present.wr_en_data_arb 66.67 66.67
tb.dut.u_reg.u_pin_in_value_ec_rst_l.wr_en_data_arb 66.67 66.67
tb.dut.u_reg.u_pin_in_value_pwrb_in.wr_en_data_arb 66.67 66.67
tb.dut.u_reg.u_pin_in_value_key0_in.wr_en_data_arb 66.67 66.67
tb.dut.u_reg.u_pin_in_value_key1_in.wr_en_data_arb 66.67 66.67
tb.dut.u_reg.u_pin_in_value_key2_in.wr_en_data_arb 66.67 66.67
tb.dut.u_reg.u_pin_in_value_lid_open.wr_en_data_arb 66.67 66.67
tb.dut.u_reg.u_intr_state.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_regwen.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_status.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_wkup_status.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_status.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_wkup_status.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_regwen.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1


Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0 + DW=16,SwAccess=0 + DW=32,SwAccess=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1 )
Line Coverage for Module self-instances :
SCORELINE
66.67 66.67
tb.dut.u_reg.u_pin_in_value_ac_present.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg.u_pin_in_value_ec_rst_l.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg.u_pin_in_value_pwrb_in.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg.u_pin_in_value_key0_in.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg.u_pin_in_value_key1_in.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg.u_pin_in_value_key2_in.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg.u_pin_in_value_lid_open.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN37100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 0 1
38 1 1
43 unreachable
44 unreachable
45 1 1


Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT13,T14,T16

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT13,T17,T19

Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%