Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.72 100.00 25.00 97.86 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 80.72 100.00 25.00 97.86 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.72 100.00 25.00 97.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.29 98.93 86.68 97.97 91.30 91.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 53.41 68.75 100.00 44.90 0.00
tlul_assert_device 99.07 100.00 100.00 97.20
u_prim_edge_detector 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
u_prim_intr_hw 100.00 100.00 100.00
u_reg 93.93 99.57 95.70 96.67 83.78
u_sysrst_ctrl_autoblock 72.30 97.06 55.56 64.29
u_sysrst_ctrl_combo 73.85 98.62 56.25 66.67
u_sysrst_ctrl_keyintr 72.93 96.77 53.85 68.18
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_sysrst_ctrl_ulp 81.81 96.30 75.00 74.14


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
66 1 1
103 1 1
104 1 1
105 1 1
106 1 1
107 1 1
108 1 1
110 1 1
288 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
295 1 1
296 1 1
313 1 1
314 1 1


Cond Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Conditions4125.00
Logical4125.00
Non-Logical00
Event00

 LINE       314
 EXPRESSION (aon_ulp_wakeup_pulse_int || aon_sysrst_ctrl_combo_intr || aon_sysrst_ctrl_key_intr)
             ------------1-----------    -------------2------------    ------------3-----------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001Not Covered
010Not Covered
100Not Covered

Toggle Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Totals 46 42 91.30
Total Bits 374 366 97.86
Total Bits 0->1 187 183 97.86
Total Bits 1->0 187 183 97.86

Ports 46 42 91.30
Port Bits 374 366 97.86
Port Bits 0->1 187 183 97.86
Port Bits 1->0 187 183 97.86

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
clk_aon_i Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
rst_ni Yes Yes T13,T36,T19 Yes T1,T4,T2 INPUT
rst_aon_ni Yes Yes T13,T36,T19 Yes T1,T4,T2 INPUT
tl_i.d_ready Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T4,T2 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T4,T2 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T37,T38,T39 Yes T37,T38,T39 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T3,T9 Yes T1,T3,T9 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
tl_o.a_ready Yes Yes T1,T4,T2 Yes T1,T4,T2 OUTPUT
tl_o.d_error Yes Yes T40,T41,T19 Yes T40,T41,T19 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T3,T9 Yes T4,T3,T9 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T3,T9 Yes T1,T4,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T4,T2 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T4,T2 Yes T1,T4,T2 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
alert_rx_i[0].ack_p Yes Yes T13,T42,T14 Yes T13,T42,T14 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T4,T2 Yes T1,T4,T2 OUTPUT
alert_tx_o[0].alert_p Yes Yes T13,T42,T14 Yes T13,T42,T14 OUTPUT
wkup_req_o Yes Yes T43 Yes T43 OUTPUT
aon_sysrst_ctrl_rst_req_o No No No OUTPUT
intr_sysrst_ctrl_o Yes Yes T36,T44,T45 Yes T36,T44,T45 OUTPUT
cio_ac_present_i No No No INPUT
cio_ec_rst_l_i Yes Yes T1,T4,T2 Yes T1,T2,T3 INPUT
cio_key0_in_i Yes Yes T1,T2,T3 Yes T1,T4,T2 INPUT
cio_key1_in_i Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
cio_key2_in_i Yes Yes T1,T4,T2 Yes T1,T4,T2 INPUT
cio_pwrb_in_i Yes Yes T1,T2,T3 Yes T1,T4,T2 INPUT
cio_lid_open_i No No No INPUT
cio_bat_disable_o Yes Yes T13,T36,T19 Yes T3,T23,T24 OUTPUT
cio_flash_wp_l_o Yes Yes T13,T19,T21 Yes T35,T46,T47 OUTPUT
cio_ec_rst_l_o Yes Yes T19,T48,T37 Yes T34,T49,T50 OUTPUT
cio_key0_out_o Yes Yes T1,T2,T3 Yes T1,T4,T2 OUTPUT
cio_key1_out_o Yes Yes T1,T4,T2 Yes T1,T4,T2 OUTPUT
cio_key2_out_o Yes Yes T1,T4,T2 Yes T1,T4,T2 OUTPUT
cio_pwrb_out_o Yes Yes T1,T2,T3 Yes T1,T4,T2 OUTPUT
cio_z3_wakeup_o Yes Yes T13,T36,T19 Yes T1,T2,T6 OUTPUT
cio_bat_disable_en_o Unreachable Unreachable Unreachable OUTPUT
cio_flash_wp_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_ec_rst_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key0_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key1_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key2_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pwrb_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_z3_wakeup_en_o Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : sysrst_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 22 22 100.00 22 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 22 22 100.00 22 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 3871954 3856890 0 0
BatOEnKnown 3871954 3856890 0 0
BatOKnown 3871954 3856890 0 0
ECRSTOEnKnown 3871954 3856890 0 0
ECRSTOKnown 3871954 3856890 0 0
FlashWpOEnKnown 3871954 3856890 0 0
FlashWpOKnown 3871954 3856890 0 0
IntrSysRstCtrlOKnown 3871954 3856890 0 0
Key0OEnKnown 3871954 3856890 0 0
Key0OKnown 3871954 3856890 0 0
Key1OEnKnown 3871954 3856890 0 0
Key1OKnown 3871954 3856890 0 0
Key2OEnKnown 3871954 3856890 0 0
Key2OKnown 3871954 3856890 0 0
OTRstOKnown 3871954 3856890 0 0
OTWkOKnown 3871954 3856890 0 0
PwrbOEnKnown 3871954 3856890 0 0
PwrbOKnown 3871954 3856890 0 0
TlOAReadyKnown 3871954 3856890 0 0
TlODValidKnown 3871954 3856890 0 0
Z3WakeupOEnKnown 3871954 3856890 0 0
Z3WwakupOKnown 3871954 3856890 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

BatOEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

BatOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

ECRSTOEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

ECRSTOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

FlashWpOEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

FlashWpOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

IntrSysRstCtrlOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Key0OEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Key0OKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Key1OEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Key1OKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Key2OEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Key2OKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

OTRstOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

OTWkOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

PwrbOEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

PwrbOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

TlOAReadyKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

TlODValidKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Z3WakeupOEnKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

Z3WwakupOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 3871954 3856890 0 0
T1 41847 41753 0 0
T2 11007 10950 0 0
T3 29027 28947 0 0
T4 2517 2428 0 0
T5 50762 50683 0 0
T6 23509 23416 0 0
T8 3336 3267 0 0
T9 6282 6183 0 0
T10 2052 1979 0 0
T11 11738 11652 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%