Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_pin
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_pin

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.72 100.00 25.00 97.86 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cfg_ac_present_i_pin 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_pin
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN9711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
87 1 1
97 1 1
107 1 1
117 1 1
127 1 1
139 8 8
143 1 1


Cond Coverage for Module : sysrst_ctrl_pin
TotalCoveredPercent
Conditions9696100.00
Logical9696100.00
Non-Logical00
Event00

 LINE       139
 EXPRESSION ((aon_enabled[0] && aon_allowed0[0] && ((!aon_values[0]))) ? 1'b0 : ((aon_enabled[0] && aon_allowed1[0] && aon_values[0]) ? 1'b1 : inputs[0]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T2

 LINE       139
 SUB-EXPRESSION (aon_enabled[0] && aon_allowed0[0] && ((!aon_values[0])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT62,T63,T64
101CoveredT5,T7,T65
110CoveredT46,T66,T67
111CoveredT1,T4,T2

 LINE       139
 SUB-EXPRESSION ((aon_enabled[0] && aon_allowed1[0] && aon_values[0]) ? 1'b1 : inputs[0])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT35,T46,T47

 LINE       139
 SUB-EXPRESSION (aon_enabled[0] && aon_allowed1[0] && aon_values[0])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT6,T29,T30
101CoveredT33,T68,T66
110CoveredT7,T69,T70
111CoveredT35,T46,T47

 LINE       139
 EXPRESSION ((aon_enabled[1] && aon_allowed0[1] && ((!aon_values[1]))) ? 1'b0 : ((aon_enabled[1] && aon_allowed1[1] && aon_values[1]) ? 1'b1 : inputs[1]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T2

 LINE       139
 SUB-EXPRESSION (aon_enabled[1] && aon_allowed0[1] && ((!aon_values[1])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT5,T35,T71
101CoveredT6,T30,T33
110CoveredT65,T72,T50
111CoveredT1,T4,T2

 LINE       139
 SUB-EXPRESSION ((aon_enabled[1] && aon_allowed1[1] && aon_values[1]) ? 1'b1 : inputs[1])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT34,T49,T50

 LINE       139
 SUB-EXPRESSION (aon_enabled[1] && aon_allowed1[1] && aon_values[1])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT29,T68,T73
101CoveredT65,T72,T74
110CoveredT6,T66,T75
111CoveredT34,T49,T50

 LINE       139
 EXPRESSION ((aon_enabled[2] && aon_allowed0[2] && ((!aon_values[2]))) ? 1'b0 : ((aon_enabled[2] && aon_allowed1[2] && aon_values[2]) ? 1'b1 : inputs[2]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT7,T46,T49

 LINE       139
 SUB-EXPRESSION (aon_enabled[2] && aon_allowed0[2] && ((!aon_values[2])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT32
101CoveredT33,T34,T73
110CoveredT30,T50,T76
111CoveredT7,T46,T49

 LINE       139
 SUB-EXPRESSION ((aon_enabled[2] && aon_allowed1[2] && aon_values[2]) ? 1'b1 : inputs[2])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT30,T50,T71

 LINE       139
 SUB-EXPRESSION (aon_enabled[2] && aon_allowed1[2] && aon_values[2])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT35,T65,T66
101CoveredT5,T74,T76
110CoveredT34,T73,T77
111CoveredT30,T50,T71

 LINE       139
 EXPRESSION ((aon_enabled[3] && aon_allowed0[3] && ((!aon_values[3]))) ? 1'b0 : ((aon_enabled[3] && aon_allowed1[3] && aon_values[3]) ? 1'b1 : inputs[3]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT31,T47,T78

 LINE       139
 SUB-EXPRESSION (aon_enabled[3] && aon_allowed0[3] && ((!aon_values[3])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT32,T34,T69
101CoveredT5,T7,T29
110CoveredT6,T65,T73
111CoveredT31,T47,T78

 LINE       139
 SUB-EXPRESSION ((aon_enabled[3] && aon_allowed1[3] && aon_values[3]) ? 1'b1 : inputs[3])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT6,T70,T63

 LINE       139
 SUB-EXPRESSION (aon_enabled[3] && aon_allowed1[3] && aon_values[3])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT33,T79,T74
101CoveredT65,T75,T73
110CoveredT7,T29,T46
111CoveredT6,T70,T63

 LINE       139
 EXPRESSION ((aon_enabled[4] && aon_allowed0[4] && ((!aon_values[4]))) ? 1'b0 : ((aon_enabled[4] && aon_allowed1[4] && aon_values[4]) ? 1'b1 : inputs[4]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT32,T35,T80

 LINE       139
 SUB-EXPRESSION (aon_enabled[4] && aon_allowed0[4] && ((!aon_values[4])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT78,T77,T81
101CoveredT46,T82,T47
110CoveredT5,T7,T30
111CoveredT32,T35,T80

 LINE       139
 SUB-EXPRESSION ((aon_enabled[4] && aon_allowed1[4] && aon_values[4]) ? 1'b1 : inputs[4])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT5,T7,T31

 LINE       139
 SUB-EXPRESSION (aon_enabled[4] && aon_allowed1[4] && aon_values[4])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT6,T33,T34
101CoveredT30,T49,T73
110CoveredT83
111CoveredT5,T7,T31

 LINE       139
 EXPRESSION ((aon_enabled[5] && aon_allowed0[5] && ((!aon_values[5]))) ? 1'b0 : ((aon_enabled[5] && aon_allowed1[5] && aon_values[5]) ? 1'b1 : inputs[5]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT34,T82,T71

 LINE       139
 SUB-EXPRESSION (aon_enabled[5] && aon_allowed0[5] && ((!aon_values[5])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT6,T79,T80
101CoveredT32,T65,T72
110CoveredT31,T33,T46
111CoveredT34,T82,T71

 LINE       139
 SUB-EXPRESSION ((aon_enabled[5] && aon_allowed1[5] && aon_values[5]) ? 1'b1 : inputs[5])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT31,T50,T84

 LINE       139
 SUB-EXPRESSION (aon_enabled[5] && aon_allowed1[5] && aon_values[5])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT7,T81,T85
101CoveredT5,T33,T46
110CoveredT32,T72,T86
111CoveredT31,T50,T84

 LINE       139
 EXPRESSION ((aon_enabled[6] && aon_allowed0[6] && ((!aon_values[6]))) ? 1'b0 : ((aon_enabled[6] && aon_allowed1[6] && aon_values[6]) ? 1'b1 : inputs[6]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT5,T30,T33

 LINE       139
 SUB-EXPRESSION (aon_enabled[6] && aon_allowed0[6] && ((!aon_values[6])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT6,T7,T32
101CoveredT69,T73,T81
110CoveredT31,T35,T68
111CoveredT5,T30,T33

 LINE       139
 SUB-EXPRESSION ((aon_enabled[6] && aon_allowed1[6] && aon_values[6]) ? 1'b1 : inputs[6])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT34,T35,T84

 LINE       139
 SUB-EXPRESSION (aon_enabled[6] && aon_allowed1[6] && aon_values[6])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT65,T72,T80
101CoveredT29,T31,T68
110CoveredT73
111CoveredT34,T35,T84

 LINE       139
 EXPRESSION ((aon_enabled[7] && aon_allowed0[7] && ((!aon_values[7]))) ? 1'b0 : ((aon_enabled[7] && aon_allowed1[7] && aon_values[7]) ? 1'b1 : inputs[7]))
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT33,T34,T78

 LINE       139
 SUB-EXPRESSION (aon_enabled[7] && aon_allowed0[7] && ((!aon_values[7])))
                 -------1------    -------2-------    ---------3--------
-1--2--3-StatusTests
011CoveredT6,T7,T68
101CoveredT5,T32,T65
110CoveredT30,T82,T86
111CoveredT33,T34,T78

 LINE       139
 SUB-EXPRESSION ((aon_enabled[7] && aon_allowed1[7] && aon_values[7]) ? 1'b1 : inputs[7])
                 --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT30,T86,T66

 LINE       139
 SUB-EXPRESSION (aon_enabled[7] && aon_allowed1[7] && aon_values[7])
                 -------1------    -------2-------    ------3------
-1--2--3-StatusTests
011CoveredT29,T31,T47
101CoveredT82,T80,T84
110CoveredT65,T46,T87
111CoveredT30,T86,T66

Branch Coverage for Module : sysrst_ctrl_pin
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 139 3 3 100.00
TERNARY 139 3 3 100.00
TERNARY 139 3 3 100.00
TERNARY 139 3 3 100.00
TERNARY 139 3 3 100.00
TERNARY 139 3 3 100.00
TERNARY 139 3 3 100.00
TERNARY 139 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 139 (((aon_enabled[0] && aon_allowed0[0]) && (!aon_values[0]))) ? -2-: 139 (((aon_enabled[0] && aon_allowed1[0]) && aon_values[0])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T35,T46,T47
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 139 (((aon_enabled[1] && aon_allowed0[1]) && (!aon_values[1]))) ? -2-: 139 (((aon_enabled[1] && aon_allowed1[1]) && aon_values[1])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T34,T49,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 139 (((aon_enabled[2] && aon_allowed0[2]) && (!aon_values[2]))) ? -2-: 139 (((aon_enabled[2] && aon_allowed1[2]) && aon_values[2])) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T46,T49
0 1 Covered T30,T50,T71
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 (((aon_enabled[3] && aon_allowed0[3]) && (!aon_values[3]))) ? -2-: 139 (((aon_enabled[3] && aon_allowed1[3]) && aon_values[3])) ?

Branches:
-1--2-StatusTests
1 - Covered T31,T47,T78
0 1 Covered T6,T70,T63
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 (((aon_enabled[4] && aon_allowed0[4]) && (!aon_values[4]))) ? -2-: 139 (((aon_enabled[4] && aon_allowed1[4]) && aon_values[4])) ?

Branches:
-1--2-StatusTests
1 - Covered T32,T35,T80
0 1 Covered T5,T7,T31
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 (((aon_enabled[5] && aon_allowed0[5]) && (!aon_values[5]))) ? -2-: 139 (((aon_enabled[5] && aon_allowed1[5]) && aon_values[5])) ?

Branches:
-1--2-StatusTests
1 - Covered T34,T82,T71
0 1 Covered T31,T50,T84
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 (((aon_enabled[6] && aon_allowed0[6]) && (!aon_values[6]))) ? -2-: 139 (((aon_enabled[6] && aon_allowed1[6]) && aon_values[6])) ?

Branches:
-1--2-StatusTests
1 - Covered T5,T30,T33
0 1 Covered T34,T35,T84
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 (((aon_enabled[7] && aon_allowed0[7]) && (!aon_values[7]))) ? -2-: 139 (((aon_enabled[7] && aon_allowed1[7]) && aon_values[7])) ?

Branches:
-1--2-StatusTests
1 - Covered T33,T34,T78
0 1 Covered T30,T86,T66
0 0 Covered T1,T4,T2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%