Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_sync_reqack
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_aon_tgl 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00
tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync 78.57 100.00 85.71 50.00



Module Instance : tb.dut.u_reg.u_aon_tgl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ec_rst_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_ac_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_lid_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_pwrb_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_ulp_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_wkup_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_invert_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_pin_allowed_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_pin_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_pin_out_value_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_intr_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_intr_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_auto_block_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_auto_block_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_com_out_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_combo_intr_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.57 100.00 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.30 100.00 90.91 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 93.33 100.00 100.00 u_key_intr_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 64719552 42712 0 0
SyncReqAckHoldReq 1607551248 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 64719552 42712 0 0
T1 42329 41 0 0
T2 11493 42 0 0
T3 29510 41 0 0
T4 2517 2 0 0
T5 50762 26 0 0
T6 23509 26 0 0
T8 3336 7 0 0
T9 6282 12 0 0
T10 2052 1 0 0
T11 11738 6 0 0
T12 482 20 0 0
T13 29450 201 0 0
T14 7771 35 0 0
T15 7752 38 0 0
T16 7752 19 0 0
T17 14611 98 0 0
T18 7752 35 0 0
T19 84512 190 0 0
T20 8949 38 0 0
T21 26619 262 0 0
T22 7809 38 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1607551248 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_aon_tgl
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_aon_tgl
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T4,T2
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T4,T2
ODD - 0 Covered T1,T4,T2
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_aon_tgl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 55421746 14758 0 0
SyncReqAckHoldReq 320614 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 14758 0 0
T1 41847 21 0 0
T2 11007 22 0 0
T3 29027 21 0 0
T4 2517 2 0 0
T5 50762 26 0 0
T6 23509 26 0 0
T8 3336 7 0 0
T9 6282 12 0 0
T10 2052 1 0 0
T11 11738 6 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 852 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 852 0 0
T13 1550 5 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 20 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 876 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 876 0 0
T13 1550 10 0 0
T14 409 1 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 9 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 20 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 869 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 869 0 0
T13 1550 4 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 7 0 0
T18 408 1 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 4 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 865 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 865 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 11 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 859 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 859 0 0
T13 1550 7 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 1 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 5 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 478 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 478 0 0
T13 1550 13 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 17 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 496 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 496 0 0
T13 1550 8 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 12 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 1895 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1895 0 0
T1 482 20 0 0
T2 486 20 0 0
T3 483 20 0 0
T12 482 20 0 0
T23 482 20 0 0
T24 482 20 0 0
T25 482 20 0 0
T26 485 20 0 0
T27 482 20 0 0
T28 485 20 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 1909 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1909 0 0
T1 482 1 0 0
T2 486 1 0 0
T3 483 1 0 0
T5 502 20 0 0
T6 503 20 0 0
T7 504 20 0 0
T12 482 1 0 0
T23 482 1 0 0
T24 482 1 0 0
T29 503 20 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 1921 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1921 0 0
T1 482 1 0 0
T2 486 1 0 0
T3 483 1 0 0
T5 502 20 0 0
T6 503 20 0 0
T7 504 20 0 0
T12 482 1 0 0
T23 482 1 0 0
T24 482 1 0 0
T29 503 20 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T7
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T5,T6,T7
ODD - 0 Covered T5,T6,T7
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 1875 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 1875 0 0
T5 502 20 0 0
T6 503 20 0 0
T7 504 20 0 0
T29 503 20 0 0
T30 502 20 0 0
T31 502 20 0 0
T32 502 20 0 0
T33 507 20 0 0
T34 502 20 0 0
T35 505 20 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 864 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 864 0 0
T13 1550 7 0 0
T14 409 1 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 20 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 892 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 892 0 0
T13 1550 18 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 6 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 14 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 871 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 871 0 0
T13 1550 6 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 8 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 15 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 881 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 881 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 1 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 10 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 902 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 902 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 11 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 12 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 883 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 883 0 0
T13 1550 13 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 1 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 16 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 885 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 885 0 0
T13 1550 11 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 10 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 21 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 853 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 853 0 0
T13 1550 14 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 2 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 17 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 860 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 860 0 0
T13 1550 13 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 6 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 10 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 855 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 855 0 0
T13 1550 10 0 0
T14 409 1 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 6 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 6 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 888 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 888 0 0
T13 1550 12 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 1 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 11 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 864 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 864 0 0
T13 1550 14 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 9 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 872 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 872 0 0
T13 1550 17 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 3 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 18 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 883 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 883 0 0
T13 1550 7 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 16 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 879 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 879 0 0
T13 1550 6 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 12 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 917 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 917 0 0
T13 1550 8 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 10 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T14,T15
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 490 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 490 0 0
T13 1550 6 0 0
T14 409 2 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 5 0 0
T18 408 1 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 8 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T13,T14,T15
EVEN 0 - Covered T1,T4,T2
ODD - 1 Covered T13,T15,T17
ODD - 0 Covered T13,T14,T15
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_prim_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 320614 520 0 0
SyncReqAckHoldReq 55421746 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 320614 520 0 0
T13 1550 10 0 0
T14 409 1 0 0
T15 408 2 0 0
T16 408 1 0 0
T17 769 7 0 0
T18 408 2 0 0
T19 4448 10 0 0
T20 471 2 0 0
T21 1401 17 0 0
T22 411 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 55421746 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%