Module Definition
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Module : prim_secded_inv_64_57_enc
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_reg.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_rsp_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_secded_inv_64_57_enc
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS1388100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%