Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.37	96.97	87.69	97.97		83.21	96.02

Total modules in report: 37

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sysrst_ctrl_csr_assert_fpv	53.41	68.75	100.00			44.90	0.00
sysrst_ctrl_autoblock	66.67	100.00	50.00			50.00
sysrst_ctrl_detect	70.32	100.00	43.75			67.22
sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=0,Sticky=1 )	83.33	100.00				66.67
sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=0 + TimerWidth=32,EdgeDetect=1,Sticky=0 )	65.83	100.00	37.50			60.00
sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=1 )	75.00					75.00
sysrst_ctrl_detect ( parameter TimerWidth=16,EdgeDetect=1,Sticky=1 + TimerWidth=16,EdgeDetect=0,Sticky=1 )	50.00		50.00
sysrst_ctrl_comboact	71.94	100.00	53.33			62.50
prim_sync_reqack	78.57	100.00				85.71	50.00
sysrst_ctrl	80.72	100.00	25.00	97.86			100.00
prim_filter_ctr	87.22	100.00	70.00			91.67
prim_filter_ctr	95.83	100.00				91.67
prim_filter_ctr ( parameter AsyncOn=0,CntWidth=16 )	80.00		80.00
prim_filter_ctr ( parameter AsyncOn=0,CntWidth=32 )	60.00		60.00
prim_subreg_arb	96.30	88.89	100.00			100.00
prim_subreg_arb	100.00					100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 + DW=16,SwAccess=0 + DW=32,SwAccess=0 )	100.00	100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1 )	66.67	66.67
prim_subreg_arb ( parameter DW=1,SwAccess=3 )	100.00	100.00
prim_subreg_arb ( parameter DW=16,SwAccess=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0 )	100.00		100.00
prim_reg_cdc	98.33	100.00	93.33			100.00	100.00
tlul_assert	99.07	100.00				100.00	97.20
tlul_data_integ_dec	100.00	100.00
sysrst_ctrl_combo	100.00	100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
sysrst_ctrl_ulp	100.00	100.00
prim_alert_sender	100.00			100.00
tlul_rsp_intg_gen	100.00	100.00					100.00
sysrst_ctrl_keyintr	100.00	100.00
prim_edge_detector	100.00	100.00				100.00
prim_subreg	100.00	100.00				100.00
prim_secded_inv_39_32_dec	100.00	100.00
prim_generic_buf	100.00	100.00
prim_intr_hw	100.00	100.00				100.00
sysrst_ctrl_reg_top	100.00	100.00	100.00			100.00	100.00
tlul_adapter_reg	100.00	100.00	100.00			100.00	100.00
prim_subreg_ext	100.00	100.00
sysrst_ctrl_pin	100.00	100.00	100.00			100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_secded_inv_64_57_dec	100.00	100.00
prim_generic_flop	100.00	100.00				100.00
tlul_data_integ_enc
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb