SYSRST_CTRL Simulation Results

Saturday January 22 2022 08:23:39 UTC

GitHub Revision: dc40cb577

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 0 50 0.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 20 20 100.00
V1 TOTAL 155 205 75.61
V2 combo_detect sysrst_ctrl_combo_detect 0 0 --
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 0 0 --
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 0 0 --
V2 pin_output_keyboard_inversion_control sysrst_ctrl_override_test 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 0 0 --
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 0 0 --
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 0 0 --
V2 alert_test sysrst_ctrl_alert_test 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 0 50 0.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_rw 20 20 100.00
sysrst_ctrl_csr_aliasing 5 5 100.00
sysrst_ctrl_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_rw 20 20 100.00
sysrst_ctrl_csr_aliasing 5 5 100.00
sysrst_ctrl_same_csr_outstanding 20 20 100.00
V2 TOTAL 190 240 79.17
V2S tl_intg_err sysrst_ctrl_tl_intg_err 20 20 100.00
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
Unmapped tests sysrst_ctrl_stress_all 0 50 0.00
TOTAL 365 565 64.60

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 12 6 5 41.67
V2S 1 1 1 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.91 98.93 86.68 97.97 -- 91.30 91.55 79.06

Failure Buckets

Past Results