SYSRST_CTRL Simulation Results

Saturday March 18 2023 07:13:12 UTC

GitHub Revision: `8498f52ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 950055979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.440s	2.110ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.060s	2.410ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.170s	2.418ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.540s	2.319ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.140s	6.012ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.270s	2.042ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.992m	65.279ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.950s	2.520ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.480s	2.118ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.270s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.950s	2.520ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	9.661m	211.654ms	49	50	98.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	5.679m	134.891ms	100	100	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	1.384m	193.823ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	30.921m	696.466ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.630s	2.511ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.520s	2.206ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	32.616m	807.289ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.790s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	46.890s	225.046ms	50	50	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.578m	36.708ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	6.918m	167.023ms	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	5.950s	2.011ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.280s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.410s	2.179ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.410s	2.179ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.140s	6.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.270s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.950s	2.520ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	36.920s	10.108ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.140s	6.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.270s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.950s	2.520ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	36.920s	10.108ms	20	20	100.00
V2		TOTAL			689	692	99.57
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.651m	42.014ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.954m	42.309ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.954m	42.309ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	3.256m	513.751ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			911	932	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.02	99.07	96.52	100.00	99.36	98.43	100.00	92.77

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 16 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 14 failures.

3.sysrst_ctrl_stress_all_with_rand_reset.227336564
Line 574, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 533313342935 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 533363342935 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 533363342935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.sysrst_ctrl_stress_all_with_rand_reset.4193069776
Line 601, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1824086309617 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 1824362174022 ps: (cip_base_vseq.sv:706) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Finished run 6/10 w/o reset
  UVM_INFO @ 1824362174022 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 6/10

... and 12 more failures.

Test sysrst_ctrl_stress_all has 2 failures.

27.sysrst_ctrl_stress_all.817379166
Line 536, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 15434847085 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 16084855484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.sysrst_ctrl_stress_all.2057094222
Line 531, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 279394348332 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 279454348332 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 279454348332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

15.sysrst_ctrl_stress_all_with_rand_reset.3788347587
Line 595, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32868157750 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 32878159875 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 7/10
  UVM_INFO @ 32881252813 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 8/10
  UVM_INFO @ 32881252813 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/789

21.sysrst_ctrl_stress_all_with_rand_reset.3332232948
Line 578, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16322060597 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16356432689 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 7/10
  UVM_INFO @ 16361249756 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 8/10
  UVM_INFO @ 16361249756 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/504

UVM_ERROR (sysrst_ctrl_base_vseq.sv:75) [sysrst_ctrl_combo_detect_vseq] Check failed (act_cycles inside {[exp_cycles - * : exp_cycles + *]}) act(50) vs exp(55) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect has 1 failures.

25.sysrst_ctrl_combo_detect.1903751366
Line 534, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest/run.log

  UVM_ERROR @ 25243542866 ps: (sysrst_ctrl_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed (act_cycles inside {[exp_cycles - 3 : exp_cycles + 3]}) act(50) vs exp(55) +/-3
  UVM_INFO @ 35342322893 ps: (sysrst_ctrl_combo_detect_vseq.sv:94) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Write data of ec_rst_ctl register:0x47
  UVM_INFO @ 35344522893 ps: (sysrst_ctrl_combo_detect_vseq.sv:99) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Write data of key_intr_debounce_ctl register:0x19
  UVM_INFO @ 35673542866 ps: (sysrst_ctrl_combo_detect_vseq.sv:164) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Value of cycles:54
  UVM_INFO @ 46103722893 ps: (sysrst_ctrl_combo_detect_vseq.sv:94) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Write data of ec_rst_ctl register:0x47

UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:114) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at Key1Idx has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

32.sysrst_ctrl_stress_all_with_rand_reset.3776182755
Line 623, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 122867457889 ps: (sysrst_ctrl_edge_detect_vseq.sv:114) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
  UVM_ERROR @ 122867457889 ps: (sysrst_ctrl_edge_detect_vseq.sv:114) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
  UVM_INFO @ 122867457889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_pin_override_vseq.sv:25) [sysrst_ctrl_pin_override_vseq] Check failed out_val == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

33.sysrst_ctrl_stress_all_with_rand_reset.3105874194
Line 575, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20819264326 ps: (sysrst_ctrl_pin_override_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Check failed out_val == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 20839643849 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 5/10
  UVM_INFO @ 20843123745 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 6/10
  UVM_INFO @ 20843123745 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/779