SYSRST_CTRL Simulation Results

Sunday March 19 2023 07:16:19 UTC

GitHub Revision: `88e220433`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2209663055

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.500s	2.113ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.080s	2.411ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.810s	2.402ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.480s	2.347ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.890s	6.010ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.490s	2.024ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.486m	33.690ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	11.480s	2.847ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.190s	2.042ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.490s	2.024ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.480s	2.847ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.550m	192.009ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.193m	201.785ms	100	100	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	14.142m	608.724ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	3.213m	158.125ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.680s	2.512ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.790s	2.205ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	18.039m	952.732ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.940s	2.609ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	13.602m	4.793s	50	50	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.759m	38.166ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	53.578m	1.354s	42	50	84.00
V2	alert_test	sysrst_ctrl_alert_test	6.210s	2.011ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.180s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.880s	2.108ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.880s	2.108ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.890s	6.010ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.490s	2.024ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.480s	2.847ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.220s	7.990ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.890s	6.010ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.490s	2.024ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.480s	2.847ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.220s	7.990ms	20	20	100.00
V2		TOTAL			684	692	98.84
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.613m	42.018ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.715m	42.308ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.715m	42.308ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	5.694m	259.199ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			908	932	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.41	96.19	100.00	98.72	98.75	99.81	92.79

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 22 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 14 failures.

3.sysrst_ctrl_stress_all_with_rand_reset.1626859351
Line 537, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11959750829 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 12132387308 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_override_vseq
  UVM_INFO @ 14132350900 ps: (sysrst_ctrl_pin_override_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Starting the body from pin_override_vseq
  UVM_INFO @ 14661224220 ps: (cip_base_vseq.sv:706) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Finished run 1/5 w/o reset

13.sysrst_ctrl_stress_all_with_rand_reset.1229018478
Line 586, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36652725272 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 36727725272 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 36727725272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test sysrst_ctrl_stress_all has 8 failures.

12.sysrst_ctrl_stress_all.1783716349
Line 585, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 162221234952 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 162371234952 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 162371234952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.sysrst_ctrl_stress_all.3388690547
Line 536, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 12668879204 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 12718879204 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 12718879204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

2.sysrst_ctrl_stress_all_with_rand_reset.3677750969
Line 595, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26686240397 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 26689013473 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 6/10
  UVM_INFO @ 26689900614 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 7/10
  UVM_INFO @ 26689900614 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/481

UVM_ERROR (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

26.sysrst_ctrl_stress_all_with_rand_reset.1913485003
Line 547, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 42457447449 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 42464965192 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 3/5
  UVM_INFO @ 42475322490 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 4/5
  UVM_INFO @ 42475322490 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/330