SYSRST_CTRL Simulation Results

Monday March 20 2023 07:20:56 UTC

GitHub Revision: `57d0a212f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2387322632

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.430s	2.113ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.640s	2.410ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.160s	2.207ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.240s	2.538ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	17.170s	6.011ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.330s	2.043ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.574m	63.354ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	11.010s	2.711ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.180s	2.046ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.330s	2.043ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.010s	2.711ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	9.730m	212.518ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.280m	204.462ms	100	100	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	9.127m	220.676ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	54.634m	1.958s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.600s	2.510ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.550s	2.190ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	9.171m	1.011s	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.960s	2.611ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.828m	3.584s	50	50	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.453m	35.900ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	8.092m	192.026ms	44	50	88.00
V2	alert_test	sysrst_ctrl_alert_test	6.080s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	5.940s	2.010ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.190s	2.052ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.190s	2.052ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	17.170s	6.011ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.330s	2.043ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.010s	2.711ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	31.660s	7.704ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	17.170s	6.011ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.330s	2.043ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.010s	2.711ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	31.660s	7.704ms	20	20	100.00
V2		TOTAL			686	692	99.13
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.658m	42.011ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.933m	42.403ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.933m	42.403ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	2.987m	906.171ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			913	932	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	99.46	95.78	100.00	98.08	98.85	99.72	88.28

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 18 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 12 failures.

2.sysrst_ctrl_stress_all_with_rand_reset.3242150019
Line 539, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12415554559 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 12515554559 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 12515554559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.sysrst_ctrl_stress_all_with_rand_reset.3403249939
Line 557, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 24342170333 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 24767170333 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 24767170333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test sysrst_ctrl_stress_all has 6 failures.

19.sysrst_ctrl_stress_all.3258735699
Line 531, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 11533328800 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 11613328800 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 11613328800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.sysrst_ctrl_stress_all.1881376794
Line 538, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 14320721812 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 14395721812 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 14395721812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:292) [sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])

has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

31.sysrst_ctrl_stress_all_with_rand_reset.4284138558
Line 610, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 91684978151 ps: (sysrst_ctrl_combo_detect_vseq.sv:292) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 91698340725 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 5/10
  UVM_INFO @ 91712510594 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 6/10
  UVM_INFO @ 91712510594 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/970