SYSRST_CTRL Simulation Results

Wednesday March 22 2023 07:11:55 UTC

GitHub Revision: `bbb91c569`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1699509302

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.440s	2.107ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.470s	2.412ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.650s	2.400ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.000s	2.499ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.190s	6.012ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.070s	2.051ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.847m	65.409ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.610s	2.325ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.730s	2.092ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.070s	2.051ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	4.610s	2.325ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	7.245m	173.375ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.495m	202.352ms	100	100	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	10.396m	240.784ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	20.118m	848.198ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.910s	2.510ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.710s	2.221ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	36.103m	1.702s	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.770s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	8.888m	2.132s	50	50	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.842m	41.345ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	9.517m	215.759ms	46	50	92.00
V2	alert_test	sysrst_ctrl_alert_test	5.880s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.120s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.610s	2.099ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.610s	2.099ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.190s	6.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.070s	2.051ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	4.610s	2.325ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.810s	9.543ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.190s	6.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.070s	2.051ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	4.610s	2.325ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.810s	9.543ms	20	20	100.00
V2		TOTAL			688	692	99.42
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.017m	22.014ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.964m	42.316ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.964m	42.316ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	6.180m	1.253s	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			912	932	97.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.24	99.54	96.12	100.00	100.00	98.92	99.53	93.60

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 18 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 14 failures.

3.sysrst_ctrl_stress_all_with_rand_reset.2381521464
Line 577, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37754955195 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 38991895610 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq
  UVM_INFO @ 40987555610 ps: (sysrst_ctrl_pin_access_vseq.sv:17) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Starting the body from pin_access_vseq
  UVM_INFO @ 41100305610 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq
  UVM_INFO @ 43097595610 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq

4.sysrst_ctrl_stress_all_with_rand_reset.4159821167
Line 532, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9666650398 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 10041650398 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 10041650398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test sysrst_ctrl_stress_all has 4 failures.

12.sysrst_ctrl_stress_all.1944488730
Line 531, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1181275422734 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 1181325422734 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 1181325422734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.sysrst_ctrl_stress_all.1161203773
Line 529, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1207675054415 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 1207755054415 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 1207755054415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

15.sysrst_ctrl_stress_all_with_rand_reset.2202117173
Line 530, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4697177554 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4700856899 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 1/5
  UVM_INFO @ 4721181510 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 2/5
  UVM_INFO @ 4721181510 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/168

UVM_ERROR (sysrst_ctrl_pin_override_vseq.sv:25) [sysrst_ctrl_pin_override_vseq] Check failed out_val == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

45.sysrst_ctrl_stress_all_with_rand_reset.1878430817
Line 585, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36720584924 ps: (sysrst_ctrl_pin_override_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Check failed out_val == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 36720584924 ps: (sysrst_ctrl_pin_override_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Check failed out_val == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 36720584924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---