SYSRST_CTRL Simulation Results

Friday March 24 2023 07:15:52 UTC

GitHub Revision: `3930c1b22`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3872236382

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.380s	2.111ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.710s	2.411ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.400s	2.199ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.670s	2.517ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	10.830s	4.015ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.570s	2.044ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.181m	33.570ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	10.820s	2.839ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.350s	2.061ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.570s	2.044ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	10.820s	2.839ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	9.137m	200.164ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.614m	185.486ms	100	100	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	7.788m	193.840ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	43.160s	62.563ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.640s	2.512ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.530s	2.245ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	22.820s	34.360ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.980s	2.615ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.003m	2.494s	50	50	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.545m	33.703ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	8.867m	214.969ms	47	50	94.00
V2	alert_test	sysrst_ctrl_alert_test	6.040s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.640s	2.015ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.970s	2.048ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.970s	2.048ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	10.830s	4.015ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.570s	2.044ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	10.820s	2.839ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	33.800s	8.426ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	10.830s	4.015ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.570s	2.044ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	10.820s	2.839ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	33.800s	8.426ms	20	20	100.00
V2		TOTAL			689	692	99.57
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.810m	42.011ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.912m	42.313ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.912m	42.313ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.612m	1.536s	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			913	932	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.87	99.41	96.09	100.00	97.44	98.78	99.63	93.76

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 16 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 13 failures.

2.sysrst_ctrl_stress_all_with_rand_reset.4104609175
Line 681, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1391509482587 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 1391569482587 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 1391569482587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sysrst_ctrl_stress_all_with_rand_reset.3721742839
Line 582, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 46503469755 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 47066873581 ps: (cip_base_vseq.sv:706) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Finished run 5/5 w/o reset
  UVM_INFO @ 47066873581 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 5/5

... and 11 more failures.

Test sysrst_ctrl_stress_all has 3 failures.

7.sysrst_ctrl_stress_all.3254695065
Line 531, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10195388918 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 10332746807 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq
  UVM_INFO @ 12327977135 ps: (sysrst_ctrl_pin_access_vseq.sv:17) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Starting the body from pin_access_vseq
  UVM_INFO @ 12342502373 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq
  UVM_INFO @ 14337904418 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq

25.sysrst_ctrl_stress_all.2458165330
Line 531, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10449979148 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 10699979148 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 10699979148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

15.sysrst_ctrl_stress_all_with_rand_reset.1730957359
Line 590, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 24762814161 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 24765287462 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 6/10
  UVM_INFO @ 24768191238 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 7/10
  UVM_INFO @ 24768191238 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/920

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

29.sysrst_ctrl_stress_all_with_rand_reset.1407447171
Line 539, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8445674126 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 8475530462 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 2/5
  UVM_INFO @ 8478459920 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 3/5
  UVM_INFO @ 8478459920 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/621

UVM_FATAL (cip_base_vseq.sv:99) [sysrst_ctrl_common_vseq] wait timeout occurred! has 1 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.sysrst_ctrl_stress_all_with_rand_reset.3201731187
    Line 532, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14020986861 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] wait timeout occurred!
  UVM_INFO @ 14020986861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```