Unified Coverage Report :: Cond split page

Go back

 LINE       6780
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T22,T40

 LINE       6780
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6780
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       6827
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T23

 LINE       6830
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6833
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Not Covered
1	1	1	Covered	T137,T138,T93

 LINE       6836
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T39,T43,T44

 LINE       6839
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T1,T2,T92

 LINE       6842
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6844
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T19,T20,T21

 LINE       6846
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T19,T20,T21

 LINE       6848
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T19,T20,T21

 LINE       6850
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T19,T20,T21

 LINE       6852
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T19,T20,T21

 LINE       6854
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6856
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T41

 LINE       6869
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T40

 LINE       6886
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T40

 LINE       6895
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T40

 LINE       6904
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T23

 LINE       6919
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Not Covered
1	1	1	Covered	T16,T22,T23

 LINE       6921
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T17,T18,T65

 LINE       6924
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T17,T18,T65

 LINE       6931
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T28,T34,T95

 LINE       6937
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T96,T97,T1

 LINE       6943
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T96,T97,T1

 LINE       6949
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T96,T97,T1

 LINE       6955
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T28,T34,T95

 LINE       6957
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T96,T97,T1

 LINE       6959
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T96,T97,T1

 LINE       6961
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T96,T97,T1

 LINE       6963
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6969
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6975
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6981
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6987
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6989
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6991
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6993
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       6995
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       7000
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       7005
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Not Covered
1	1	1	Covered	T16,T22,T24

 LINE       7010
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Not Covered
1	1	1	Covered	T16,T22,T24

 LINE       7015
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T24

 LINE       7020
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T18
1	0	1	Covered	T16,T17,T18
1	1	0	Covered	T4,T53,T56
1	1	1	Covered	T16,T22,T23

 LINE       7242
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Unreachable
1	0	Covered	T16,T17,T18