Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T27 |
9 |
|
T16 |
6 |
|
T19 |
8 |
| auto[1] |
949 |
1 |
|
|
T27 |
11 |
|
T16 |
14 |
|
T19 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T27 |
9 |
|
T16 |
11 |
|
T19 |
11 |
| auto[1] |
912 |
1 |
|
|
T27 |
11 |
|
T16 |
9 |
|
T19 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T27 |
6 |
|
T16 |
8 |
|
T19 |
10 |
| auto[1] |
916 |
1 |
|
|
T27 |
14 |
|
T16 |
12 |
|
T19 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T27 |
8 |
|
T16 |
7 |
|
T19 |
13 |
| auto[1] |
928 |
1 |
|
|
T27 |
12 |
|
T16 |
13 |
|
T19 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T27 |
13 |
|
T16 |
12 |
|
T19 |
7 |
| auto[1] |
925 |
1 |
|
|
T27 |
7 |
|
T16 |
8 |
|
T19 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T27 |
8 |
|
T16 |
7 |
|
T19 |
8 |
| auto[1] |
953 |
1 |
|
|
T27 |
12 |
|
T16 |
13 |
|
T19 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T27 |
7 |
|
T16 |
12 |
|
T19 |
10 |
| auto[1] |
908 |
1 |
|
|
T27 |
13 |
|
T16 |
8 |
|
T19 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T27 |
11 |
|
T16 |
13 |
|
T19 |
13 |
| auto[1] |
910 |
1 |
|
|
T27 |
9 |
|
T16 |
7 |
|
T19 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T27 |
7 |
|
T16 |
7 |
|
T19 |
11 |
| auto[1] |
952 |
1 |
|
|
T27 |
13 |
|
T16 |
13 |
|
T19 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
916 |
1 |
|
|
T27 |
9 |
|
T16 |
10 |
|
T19 |
7 |
| auto[1] |
884 |
1 |
|
|
T27 |
11 |
|
T16 |
10 |
|
T19 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T27 |
12 |
|
T16 |
11 |
|
T19 |
10 |
| auto[1] |
921 |
1 |
|
|
T27 |
8 |
|
T16 |
9 |
|
T19 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
907 |
1 |
|
|
T27 |
5 |
|
T16 |
8 |
|
T19 |
9 |
| auto[1] |
893 |
1 |
|
|
T27 |
15 |
|
T16 |
12 |
|
T19 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T27 |
11 |
|
T16 |
12 |
|
T19 |
11 |
| auto[1] |
887 |
1 |
|
|
T27 |
9 |
|
T16 |
8 |
|
T19 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T27 |
9 |
|
T16 |
11 |
|
T19 |
11 |
| auto[1] |
912 |
1 |
|
|
T27 |
11 |
|
T16 |
9 |
|
T19 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T27 |
12 |
|
T16 |
9 |
|
T19 |
10 |
| auto[1] |
890 |
1 |
|
|
T27 |
8 |
|
T16 |
11 |
|
T19 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T27 |
14 |
|
T16 |
12 |
|
T19 |
11 |
| auto[1] |
896 |
1 |
|
|
T27 |
6 |
|
T16 |
8 |
|
T19 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T27 |
10 |
|
T16 |
9 |
|
T19 |
12 |
| auto[1] |
902 |
1 |
|
|
T27 |
10 |
|
T16 |
11 |
|
T19 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
908 |
1 |
|
|
T27 |
9 |
|
T16 |
8 |
|
T19 |
9 |
| auto[1] |
892 |
1 |
|
|
T27 |
11 |
|
T16 |
12 |
|
T19 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T27 |
11 |
|
T16 |
9 |
|
T19 |
13 |
| auto[1] |
918 |
1 |
|
|
T27 |
9 |
|
T16 |
11 |
|
T19 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T27 |
7 |
|
T16 |
12 |
|
T19 |
14 |
| auto[1] |
924 |
1 |
|
|
T27 |
13 |
|
T16 |
8 |
|
T19 |
6 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T27 |
11 |
|
T16 |
10 |
|
T19 |
9 |
| auto[1] |
929 |
1 |
|
|
T27 |
9 |
|
T16 |
10 |
|
T19 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
870 |
1 |
|
|
T27 |
11 |
|
T16 |
11 |
|
T19 |
7 |
| auto[1] |
930 |
1 |
|
|
T27 |
9 |
|
T16 |
9 |
|
T19 |
13 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
965 |
1 |
|
|
T27 |
10 |
|
T16 |
12 |
|
T19 |
14 |
| auto[1] |
835 |
1 |
|
|
T27 |
10 |
|
T16 |
8 |
|
T19 |
6 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
907 |
1 |
|
|
T27 |
5 |
|
T16 |
8 |
|
T19 |
9 |
| auto[1] |
893 |
1 |
|
|
T27 |
15 |
|
T16 |
12 |
|
T19 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
461 |
1 |
|
|
T27 |
2 |
|
T16 |
5 |
|
T19 |
7 |
| auto[0] |
auto[1] |
449 |
1 |
|
|
T27 |
10 |
|
T16 |
4 |
|
T19 |
3 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T27 |
4 |
|
T16 |
3 |
|
T19 |
3 |
| auto[1] |
auto[1] |
467 |
1 |
|
|
T27 |
4 |
|
T16 |
8 |
|
T19 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
452 |
1 |
|
|
T27 |
4 |
|
T16 |
6 |
|
T19 |
9 |
| auto[0] |
auto[1] |
452 |
1 |
|
|
T27 |
10 |
|
T16 |
6 |
|
T19 |
2 |
| auto[1] |
auto[0] |
420 |
1 |
|
|
T27 |
4 |
|
T16 |
1 |
|
T19 |
4 |
| auto[1] |
auto[1] |
476 |
1 |
|
|
T27 |
2 |
|
T16 |
7 |
|
T19 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
438 |
1 |
|
|
T27 |
5 |
|
T16 |
6 |
|
T19 |
5 |
| auto[0] |
auto[1] |
460 |
1 |
|
|
T27 |
5 |
|
T16 |
3 |
|
T19 |
7 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T27 |
8 |
|
T16 |
6 |
|
T19 |
2 |
| auto[1] |
auto[1] |
465 |
1 |
|
|
T27 |
2 |
|
T16 |
5 |
|
T19 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
429 |
1 |
|
|
T27 |
2 |
|
T16 |
3 |
|
T19 |
4 |
| auto[0] |
auto[1] |
479 |
1 |
|
|
T27 |
7 |
|
T16 |
5 |
|
T19 |
5 |
| auto[1] |
auto[0] |
418 |
1 |
|
|
T27 |
6 |
|
T16 |
4 |
|
T19 |
4 |
| auto[1] |
auto[1] |
474 |
1 |
|
|
T27 |
5 |
|
T16 |
8 |
|
T19 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
447 |
1 |
|
|
T27 |
4 |
|
T16 |
6 |
|
T19 |
7 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T27 |
7 |
|
T16 |
3 |
|
T19 |
6 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T27 |
3 |
|
T16 |
6 |
|
T19 |
3 |
| auto[1] |
auto[1] |
473 |
1 |
|
|
T27 |
6 |
|
T16 |
5 |
|
T19 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
443 |
1 |
|
|
T27 |
4 |
|
T16 |
8 |
|
T19 |
9 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T27 |
3 |
|
T16 |
4 |
|
T19 |
5 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T27 |
7 |
|
T16 |
5 |
|
T19 |
4 |
| auto[1] |
auto[1] |
477 |
1 |
|
|
T27 |
6 |
|
T16 |
3 |
|
T19 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T27 |
7 |
|
T16 |
6 |
|
T19 |
4 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T27 |
4 |
|
T16 |
5 |
|
T19 |
3 |
| auto[1] |
auto[0] |
482 |
1 |
|
|
T27 |
2 |
|
T16 |
4 |
|
T19 |
3 |
| auto[1] |
auto[1] |
448 |
1 |
|
|
T27 |
7 |
|
T16 |
5 |
|
T19 |
10 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
463 |
1 |
|
|
T27 |
8 |
|
T16 |
7 |
|
T19 |
9 |
| auto[0] |
auto[1] |
502 |
1 |
|
|
T27 |
2 |
|
T16 |
5 |
|
T19 |
5 |
| auto[1] |
auto[0] |
416 |
1 |
|
|
T27 |
4 |
|
T16 |
4 |
|
T19 |
1 |
| auto[1] |
auto[1] |
419 |
1 |
|
|
T27 |
6 |
|
T16 |
4 |
|
T19 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T27 |
4 |
|
T16 |
6 |
|
T19 |
5 |
| auto[0] |
auto[1] |
472 |
1 |
|
|
T27 |
7 |
|
T16 |
6 |
|
T19 |
6 |
| auto[1] |
auto[0] |
410 |
1 |
|
|
T27 |
5 |
|
T19 |
3 |
|
T84 |
4 |
| auto[1] |
auto[1] |
477 |
1 |
|
|
T27 |
4 |
|
T16 |
8 |
|
T19 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
888 |
1 |
|
|
T27 |
9 |
|
T16 |
11 |
|
T19 |
11 |
| auto[1] |
auto[1] |
912 |
1 |
|
|
T27 |
11 |
|
T16 |
9 |
|
T19 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T27 |
4 |
|
T16 |
3 |
|
T19 |
6 |
| auto[0] |
auto[1] |
463 |
1 |
|
|
T27 |
7 |
|
T16 |
7 |
|
T19 |
3 |
| auto[1] |
auto[0] |
440 |
1 |
|
|
T27 |
3 |
|
T16 |
4 |
|
T19 |
5 |
| auto[1] |
auto[1] |
489 |
1 |
|
|
T27 |
6 |
|
T16 |
6 |
|
T19 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
907 |
1 |
|
|
T27 |
5 |
|
T16 |
8 |
|
T19 |
9 |
| auto[1] |
auto[1] |
893 |
1 |
|
|
T27 |
15 |
|
T16 |
12 |
|
T19 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T27 |
9 |
|
T16 |
13 |
|
T19 |
7 |
| auto[1] |
209 |
1 |
|
|
T27 |
11 |
|
T16 |
7 |
|
T19 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
207 |
1 |
|
|
T27 |
15 |
|
T16 |
14 |
|
T19 |
6 |
| auto[1] |
204 |
1 |
|
|
T27 |
5 |
|
T16 |
6 |
|
T19 |
14 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
199 |
1 |
|
|
T27 |
9 |
|
T16 |
10 |
|
T19 |
8 |
| auto[1] |
212 |
1 |
|
|
T27 |
11 |
|
T16 |
10 |
|
T19 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
211 |
1 |
|
|
T27 |
10 |
|
T16 |
12 |
|
T19 |
12 |
| auto[1] |
200 |
1 |
|
|
T27 |
10 |
|
T16 |
8 |
|
T19 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T27 |
9 |
|
T16 |
15 |
|
T19 |
7 |
| auto[1] |
208 |
1 |
|
|
T27 |
11 |
|
T16 |
5 |
|
T19 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
219 |
1 |
|
|
T27 |
12 |
|
T16 |
11 |
|
T19 |
9 |
| auto[1] |
192 |
1 |
|
|
T27 |
8 |
|
T16 |
9 |
|
T19 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
201 |
1 |
|
|
T27 |
7 |
|
T16 |
9 |
|
T19 |
11 |
| auto[1] |
210 |
1 |
|
|
T27 |
13 |
|
T16 |
11 |
|
T19 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T27 |
10 |
|
T16 |
7 |
|
T19 |
7 |
| auto[1] |
221 |
1 |
|
|
T27 |
10 |
|
T16 |
13 |
|
T19 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
191 |
1 |
|
|
T27 |
11 |
|
T16 |
9 |
|
T19 |
7 |
| auto[1] |
220 |
1 |
|
|
T27 |
9 |
|
T16 |
11 |
|
T19 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
212 |
1 |
|
|
T27 |
11 |
|
T16 |
8 |
|
T19 |
13 |
| auto[1] |
199 |
1 |
|
|
T27 |
9 |
|
T16 |
12 |
|
T19 |
7 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T27 |
12 |
|
T16 |
7 |
|
T19 |
11 |
| auto[1] |
208 |
1 |
|
|
T27 |
8 |
|
T16 |
13 |
|
T19 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
209 |
1 |
|
|
T27 |
13 |
|
T16 |
8 |
|
T19 |
11 |
| auto[1] |
202 |
1 |
|
|
T27 |
7 |
|
T16 |
12 |
|
T19 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
205 |
1 |
|
|
T27 |
9 |
|
T16 |
11 |
|
T19 |
11 |
| auto[1] |
206 |
1 |
|
|
T27 |
11 |
|
T16 |
9 |
|
T19 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
207 |
1 |
|
|
T27 |
15 |
|
T16 |
14 |
|
T19 |
6 |
| auto[1] |
204 |
1 |
|
|
T27 |
5 |
|
T16 |
6 |
|
T19 |
14 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
221 |
1 |
|
|
T27 |
6 |
|
T16 |
7 |
|
T19 |
12 |
| auto[1] |
190 |
1 |
|
|
T27 |
14 |
|
T16 |
13 |
|
T19 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
213 |
1 |
|
|
T27 |
9 |
|
T16 |
15 |
|
T19 |
8 |
| auto[1] |
198 |
1 |
|
|
T27 |
11 |
|
T16 |
5 |
|
T19 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
192 |
1 |
|
|
T27 |
14 |
|
T16 |
8 |
|
T19 |
4 |
| auto[1] |
219 |
1 |
|
|
T27 |
6 |
|
T16 |
12 |
|
T19 |
16 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T27 |
9 |
|
T16 |
10 |
|
T19 |
10 |
| auto[1] |
217 |
1 |
|
|
T27 |
11 |
|
T16 |
10 |
|
T19 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
225 |
1 |
|
|
T27 |
14 |
|
T16 |
8 |
|
T19 |
9 |
| auto[1] |
186 |
1 |
|
|
T27 |
6 |
|
T16 |
12 |
|
T19 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
222 |
1 |
|
|
T27 |
11 |
|
T16 |
12 |
|
T19 |
7 |
| auto[1] |
189 |
1 |
|
|
T27 |
9 |
|
T16 |
8 |
|
T19 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
207 |
1 |
|
|
T27 |
12 |
|
T16 |
13 |
|
T19 |
8 |
| auto[1] |
204 |
1 |
|
|
T27 |
8 |
|
T16 |
7 |
|
T19 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
212 |
1 |
|
|
T27 |
9 |
|
T16 |
8 |
|
T19 |
9 |
| auto[1] |
199 |
1 |
|
|
T27 |
11 |
|
T16 |
12 |
|
T19 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T27 |
10 |
|
T16 |
9 |
|
T19 |
9 |
| auto[1] |
208 |
1 |
|
|
T27 |
10 |
|
T16 |
11 |
|
T19 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
209 |
1 |
|
|
T27 |
13 |
|
T16 |
8 |
|
T19 |
11 |
| auto[1] |
202 |
1 |
|
|
T27 |
7 |
|
T16 |
12 |
|
T19 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
116 |
1 |
|
|
T27 |
3 |
|
T16 |
4 |
|
T19 |
4 |
| auto[0] |
auto[1] |
105 |
1 |
|
|
T27 |
3 |
|
T16 |
3 |
|
T19 |
8 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T27 |
6 |
|
T16 |
6 |
|
T19 |
4 |
| auto[1] |
auto[1] |
107 |
1 |
|
|
T27 |
8 |
|
T16 |
7 |
|
T19 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
118 |
1 |
|
|
T27 |
5 |
|
T16 |
9 |
|
T19 |
4 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T27 |
4 |
|
T16 |
6 |
|
T19 |
4 |
| auto[1] |
auto[0] |
93 |
1 |
|
|
T27 |
5 |
|
T16 |
3 |
|
T19 |
8 |
| auto[1] |
auto[1] |
105 |
1 |
|
|
T27 |
6 |
|
T16 |
2 |
|
T19 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
91 |
1 |
|
|
T27 |
5 |
|
T16 |
7 |
|
T19 |
1 |
| auto[0] |
auto[1] |
101 |
1 |
|
|
T27 |
9 |
|
T16 |
1 |
|
T19 |
3 |
| auto[1] |
auto[0] |
112 |
1 |
|
|
T27 |
4 |
|
T16 |
8 |
|
T19 |
6 |
| auto[1] |
auto[1] |
107 |
1 |
|
|
T27 |
2 |
|
T16 |
4 |
|
T19 |
10 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
100 |
1 |
|
|
T27 |
4 |
|
T16 |
6 |
|
T19 |
5 |
| auto[0] |
auto[1] |
94 |
1 |
|
|
T27 |
5 |
|
T16 |
4 |
|
T19 |
5 |
| auto[1] |
auto[0] |
119 |
1 |
|
|
T27 |
8 |
|
T16 |
5 |
|
T19 |
4 |
| auto[1] |
auto[1] |
98 |
1 |
|
|
T27 |
3 |
|
T16 |
5 |
|
T19 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
113 |
1 |
|
|
T27 |
7 |
|
T16 |
5 |
|
T19 |
5 |
| auto[0] |
auto[1] |
112 |
1 |
|
|
T27 |
7 |
|
T16 |
3 |
|
T19 |
4 |
| auto[1] |
auto[0] |
88 |
1 |
|
|
T16 |
4 |
|
T19 |
6 |
|
T41 |
5 |
| auto[1] |
auto[1] |
98 |
1 |
|
|
T27 |
6 |
|
T16 |
8 |
|
T19 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
106 |
1 |
|
|
T27 |
7 |
|
T16 |
6 |
|
T19 |
2 |
| auto[0] |
auto[1] |
116 |
1 |
|
|
T27 |
4 |
|
T16 |
6 |
|
T19 |
5 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T27 |
3 |
|
T16 |
1 |
|
T19 |
5 |
| auto[1] |
auto[1] |
105 |
1 |
|
|
T27 |
6 |
|
T16 |
7 |
|
T19 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
109 |
1 |
|
|
T27 |
4 |
|
T16 |
7 |
|
T19 |
6 |
| auto[0] |
auto[1] |
103 |
1 |
|
|
T27 |
5 |
|
T16 |
1 |
|
T19 |
3 |
| auto[1] |
auto[0] |
103 |
1 |
|
|
T27 |
7 |
|
T16 |
1 |
|
T19 |
7 |
| auto[1] |
auto[1] |
96 |
1 |
|
|
T27 |
4 |
|
T16 |
11 |
|
T19 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
100 |
1 |
|
|
T27 |
5 |
|
T16 |
7 |
|
T19 |
5 |
| auto[0] |
auto[1] |
103 |
1 |
|
|
T27 |
5 |
|
T16 |
2 |
|
T19 |
4 |
| auto[1] |
auto[0] |
103 |
1 |
|
|
T27 |
7 |
|
T19 |
6 |
|
T41 |
6 |
| auto[1] |
auto[1] |
105 |
1 |
|
|
T27 |
3 |
|
T16 |
11 |
|
T19 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T27 |
3 |
|
T16 |
7 |
|
T19 |
3 |
| auto[0] |
auto[1] |
102 |
1 |
|
|
T27 |
6 |
|
T16 |
4 |
|
T19 |
8 |
| auto[1] |
auto[0] |
99 |
1 |
|
|
T27 |
6 |
|
T16 |
6 |
|
T19 |
4 |
| auto[1] |
auto[1] |
107 |
1 |
|
|
T27 |
5 |
|
T16 |
3 |
|
T19 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
207 |
1 |
|
|
T27 |
15 |
|
T16 |
14 |
|
T19 |
6 |
| auto[1] |
auto[1] |
204 |
1 |
|
|
T27 |
5 |
|
T16 |
6 |
|
T19 |
14 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T27 |
7 |
|
T16 |
9 |
|
T19 |
3 |
| auto[0] |
auto[1] |
104 |
1 |
|
|
T27 |
5 |
|
T16 |
4 |
|
T19 |
5 |
| auto[1] |
auto[0] |
88 |
1 |
|
|
T27 |
4 |
|
T19 |
4 |
|
T41 |
3 |
| auto[1] |
auto[1] |
116 |
1 |
|
|
T27 |
4 |
|
T16 |
7 |
|
T19 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
209 |
1 |
|
|
T27 |
13 |
|
T16 |
8 |
|
T19 |
11 |
| auto[1] |
auto[1] |
202 |
1 |
|
|
T27 |
7 |
|
T16 |
12 |
|
T19 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T19 |
13 |
|
T41 |
8 |
|
T42 |
9 |
| auto[1] |
96 |
1 |
|
|
T19 |
7 |
|
T41 |
12 |
|
T42 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T19 |
9 |
|
T41 |
9 |
|
T42 |
11 |
| auto[1] |
93 |
1 |
|
|
T19 |
11 |
|
T41 |
11 |
|
T42 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T19 |
12 |
|
T41 |
13 |
|
T42 |
11 |
| auto[1] |
89 |
1 |
|
|
T19 |
8 |
|
T41 |
7 |
|
T42 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T19 |
10 |
|
T41 |
8 |
|
T42 |
9 |
| auto[1] |
97 |
1 |
|
|
T19 |
10 |
|
T41 |
12 |
|
T42 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T19 |
12 |
|
T41 |
12 |
|
T42 |
13 |
| auto[1] |
84 |
1 |
|
|
T19 |
8 |
|
T41 |
8 |
|
T42 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T19 |
10 |
|
T41 |
9 |
|
T42 |
12 |
| auto[1] |
89 |
1 |
|
|
T19 |
10 |
|
T41 |
11 |
|
T42 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
86 |
1 |
|
|
T19 |
11 |
|
T41 |
13 |
|
T42 |
5 |
| auto[1] |
94 |
1 |
|
|
T19 |
9 |
|
T41 |
7 |
|
T42 |
15 |