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 LINE       6847
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T27
1	1	0	Covered	T42,T288,T289
1	1	1	Covered	T7,T14,T18

 LINE       6849
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T25
1	1	0	Covered	T289,T290,T293
1	1	1	Covered	T7,T18,T19

 LINE       6851
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T1,T3,T4

 LINE       6853
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T24,T4
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T1,T24,T46

 LINE       6866
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T24,T4
1	1	0	Covered	T287,T288,T289
1	1	1	Covered	T1,T24,T25

 LINE       6883
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T289,T294,T295
1	1	1	Covered	T5,T1,T3

 LINE       6892
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T25
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T1,T25,T30

 LINE       6901
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T42,T288,T290
1	1	1	Covered	T2,T8,T9

 LINE       6916
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T5,T1,T2

 LINE       6918
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T26
1	1	0	Covered	T293,T294,T296
1	1	1	Covered	T26,T47,T8

 LINE       6921
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T26
1	1	0	Covered	T288,T290,T294
1	1	1	Covered	T26,T47,T8

 LINE       6928
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T290,T294
1	1	1	Covered	T27,T48,T6

 LINE       6934
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T27,T48,T6

 LINE       6940
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T27,T48,T6

 LINE       6946
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T290,T294
1	1	1	Covered	T27,T48,T6

 LINE       6952
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T27
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T27,T48,T6

 LINE       6954
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T27
1	1	0	Covered	T289,T290,T293
1	1	1	Covered	T27,T48,T6

 LINE       6956
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T27
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T27,T48,T6

 LINE       6958
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T4,T27
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T27,T48,T6

 LINE       6960
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T285,T288,T289
1	1	1	Covered	T5,T1,T3

 LINE       6966
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T5,T3,T4

 LINE       6972
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T293,T294
1	1	1	Covered	T5,T3,T4

 LINE       6978
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T5,T3,T4

 LINE       6984
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T5,T1,T3

 LINE       6986
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T290,T294
1	1	1	Covered	T5,T3,T4

 LINE       6988
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T5,T3,T4

 LINE       6990
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T132,T44,T288
1	1	1	Covered	T5,T3,T4

 LINE       6992
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T293
1	1	1	Covered	T5,T1,T3

 LINE       6997
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T290,T293
1	1	1	Covered	T5,T3,T4

 LINE       7002
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T5,T3,T4

 LINE       7007
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T290,T294,T297
1	1	1	Covered	T5,T3,T4

 LINE       7012
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T5,T1,T3
1	1	0	Covered	T288,T289,T290
1	1	1	Covered	T1,T3,T4

 LINE       7017
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T289,T290,T293
1	1	1	Covered	T2,T8,T9

 LINE       7239
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T2