Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T24 |
9 |
|
T3 |
12 |
|
T25 |
11 |
| auto[1] |
799 |
1 |
|
|
T24 |
11 |
|
T3 |
8 |
|
T25 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T24 |
8 |
|
T3 |
9 |
|
T25 |
8 |
| auto[1] |
792 |
1 |
|
|
T24 |
12 |
|
T3 |
11 |
|
T25 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
762 |
1 |
|
|
T24 |
10 |
|
T3 |
8 |
|
T25 |
12 |
| auto[1] |
838 |
1 |
|
|
T24 |
10 |
|
T3 |
12 |
|
T25 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T24 |
9 |
|
T3 |
5 |
|
T25 |
4 |
| auto[1] |
777 |
1 |
|
|
T24 |
11 |
|
T3 |
15 |
|
T25 |
16 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T24 |
9 |
|
T3 |
9 |
|
T25 |
15 |
| auto[1] |
769 |
1 |
|
|
T24 |
11 |
|
T3 |
11 |
|
T25 |
5 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T24 |
9 |
|
T3 |
10 |
|
T25 |
11 |
| auto[1] |
764 |
1 |
|
|
T24 |
11 |
|
T3 |
10 |
|
T25 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T24 |
5 |
|
T3 |
6 |
|
T25 |
12 |
| auto[1] |
811 |
1 |
|
|
T24 |
15 |
|
T3 |
14 |
|
T25 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
786 |
1 |
|
|
T24 |
12 |
|
T3 |
13 |
|
T25 |
13 |
| auto[1] |
814 |
1 |
|
|
T24 |
8 |
|
T3 |
7 |
|
T25 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
796 |
1 |
|
|
T24 |
9 |
|
T3 |
11 |
|
T25 |
7 |
| auto[1] |
804 |
1 |
|
|
T24 |
11 |
|
T3 |
9 |
|
T25 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
805 |
1 |
|
|
T24 |
6 |
|
T3 |
12 |
|
T25 |
8 |
| auto[1] |
795 |
1 |
|
|
T24 |
14 |
|
T3 |
8 |
|
T25 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T24 |
8 |
|
T3 |
10 |
|
T25 |
15 |
| auto[1] |
767 |
1 |
|
|
T24 |
12 |
|
T3 |
10 |
|
T25 |
5 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T24 |
9 |
|
T3 |
11 |
|
T25 |
11 |
| auto[1] |
792 |
1 |
|
|
T24 |
11 |
|
T3 |
9 |
|
T25 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T24 |
6 |
|
T3 |
13 |
|
T25 |
11 |
| auto[1] |
787 |
1 |
|
|
T24 |
14 |
|
T3 |
7 |
|
T25 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T24 |
8 |
|
T3 |
9 |
|
T25 |
8 |
| auto[1] |
792 |
1 |
|
|
T24 |
12 |
|
T3 |
11 |
|
T25 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T24 |
14 |
|
T3 |
9 |
|
T25 |
11 |
| auto[1] |
767 |
1 |
|
|
T24 |
6 |
|
T3 |
11 |
|
T25 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T24 |
11 |
|
T3 |
10 |
|
T25 |
7 |
| auto[1] |
780 |
1 |
|
|
T24 |
9 |
|
T3 |
10 |
|
T25 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T24 |
8 |
|
T3 |
17 |
|
T25 |
8 |
| auto[1] |
786 |
1 |
|
|
T24 |
12 |
|
T3 |
3 |
|
T25 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T24 |
14 |
|
T3 |
10 |
|
T25 |
10 |
| auto[1] |
801 |
1 |
|
|
T24 |
6 |
|
T3 |
10 |
|
T25 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T24 |
14 |
|
T3 |
9 |
|
T25 |
11 |
| auto[1] |
772 |
1 |
|
|
T24 |
6 |
|
T3 |
11 |
|
T25 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
767 |
1 |
|
|
T24 |
13 |
|
T3 |
10 |
|
T25 |
10 |
| auto[1] |
833 |
1 |
|
|
T24 |
7 |
|
T3 |
10 |
|
T25 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T24 |
7 |
|
T3 |
7 |
|
T25 |
9 |
| auto[1] |
780 |
1 |
|
|
T24 |
13 |
|
T3 |
13 |
|
T25 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T24 |
12 |
|
T3 |
8 |
|
T25 |
13 |
| auto[1] |
779 |
1 |
|
|
T24 |
8 |
|
T3 |
12 |
|
T25 |
7 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
783 |
1 |
|
|
T24 |
10 |
|
T3 |
14 |
|
T25 |
10 |
| auto[1] |
817 |
1 |
|
|
T24 |
10 |
|
T3 |
6 |
|
T25 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T24 |
9 |
|
T3 |
11 |
|
T25 |
11 |
| auto[1] |
792 |
1 |
|
|
T24 |
11 |
|
T3 |
9 |
|
T25 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
386 |
1 |
|
|
T24 |
7 |
|
T3 |
3 |
|
T25 |
6 |
| auto[0] |
auto[1] |
447 |
1 |
|
|
T24 |
7 |
|
T3 |
6 |
|
T25 |
5 |
| auto[1] |
auto[0] |
376 |
1 |
|
|
T24 |
3 |
|
T3 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
391 |
1 |
|
|
T24 |
3 |
|
T3 |
6 |
|
T25 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
410 |
1 |
|
|
T24 |
5 |
|
T3 |
2 |
|
T53 |
5 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T24 |
6 |
|
T3 |
8 |
|
T25 |
7 |
| auto[1] |
auto[0] |
413 |
1 |
|
|
T24 |
4 |
|
T3 |
3 |
|
T25 |
4 |
| auto[1] |
auto[1] |
367 |
1 |
|
|
T24 |
5 |
|
T3 |
7 |
|
T25 |
9 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
401 |
1 |
|
|
T24 |
3 |
|
T3 |
6 |
|
T25 |
6 |
| auto[0] |
auto[1] |
413 |
1 |
|
|
T24 |
5 |
|
T3 |
11 |
|
T25 |
2 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T24 |
6 |
|
T3 |
3 |
|
T25 |
9 |
| auto[1] |
auto[1] |
356 |
1 |
|
|
T24 |
6 |
|
T25 |
3 |
|
T53 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
396 |
1 |
|
|
T24 |
6 |
|
T3 |
3 |
|
T25 |
5 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T24 |
8 |
|
T3 |
7 |
|
T25 |
5 |
| auto[1] |
auto[0] |
440 |
1 |
|
|
T24 |
3 |
|
T3 |
7 |
|
T25 |
6 |
| auto[1] |
auto[1] |
361 |
1 |
|
|
T24 |
3 |
|
T3 |
3 |
|
T25 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T24 |
3 |
|
T3 |
2 |
|
T25 |
6 |
| auto[0] |
auto[1] |
417 |
1 |
|
|
T24 |
11 |
|
T3 |
7 |
|
T25 |
5 |
| auto[1] |
auto[0] |
378 |
1 |
|
|
T24 |
2 |
|
T3 |
4 |
|
T25 |
6 |
| auto[1] |
auto[1] |
394 |
1 |
|
|
T24 |
4 |
|
T3 |
7 |
|
T25 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
379 |
1 |
|
|
T24 |
6 |
|
T3 |
6 |
|
T25 |
6 |
| auto[0] |
auto[1] |
388 |
1 |
|
|
T24 |
7 |
|
T3 |
4 |
|
T25 |
4 |
| auto[1] |
auto[0] |
407 |
1 |
|
|
T24 |
6 |
|
T3 |
7 |
|
T25 |
7 |
| auto[1] |
auto[1] |
426 |
1 |
|
|
T24 |
1 |
|
T3 |
3 |
|
T25 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
410 |
1 |
|
|
T24 |
2 |
|
T3 |
3 |
|
T25 |
4 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T24 |
10 |
|
T3 |
5 |
|
T25 |
9 |
| auto[1] |
auto[0] |
395 |
1 |
|
|
T24 |
4 |
|
T3 |
9 |
|
T25 |
4 |
| auto[1] |
auto[1] |
384 |
1 |
|
|
T24 |
4 |
|
T3 |
3 |
|
T25 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
405 |
1 |
|
|
T24 |
2 |
|
T3 |
5 |
|
T25 |
6 |
| auto[0] |
auto[1] |
378 |
1 |
|
|
T24 |
8 |
|
T3 |
9 |
|
T25 |
4 |
| auto[1] |
auto[0] |
428 |
1 |
|
|
T24 |
6 |
|
T3 |
5 |
|
T25 |
9 |
| auto[1] |
auto[1] |
389 |
1 |
|
|
T24 |
4 |
|
T3 |
1 |
|
T25 |
1 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
399 |
1 |
|
|
T24 |
3 |
|
T3 |
8 |
|
T25 |
6 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T24 |
3 |
|
T3 |
5 |
|
T25 |
5 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T24 |
6 |
|
T3 |
4 |
|
T25 |
5 |
| auto[1] |
auto[1] |
385 |
1 |
|
|
T24 |
8 |
|
T3 |
3 |
|
T25 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
808 |
1 |
|
|
T24 |
8 |
|
T3 |
9 |
|
T25 |
8 |
| auto[1] |
auto[1] |
792 |
1 |
|
|
T24 |
12 |
|
T3 |
11 |
|
T25 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
410 |
1 |
|
|
T24 |
4 |
|
T3 |
3 |
|
T25 |
3 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T24 |
3 |
|
T3 |
4 |
|
T25 |
6 |
| auto[1] |
auto[0] |
386 |
1 |
|
|
T24 |
5 |
|
T3 |
8 |
|
T25 |
4 |
| auto[1] |
auto[1] |
394 |
1 |
|
|
T24 |
8 |
|
T3 |
5 |
|
T25 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
808 |
1 |
|
|
T24 |
9 |
|
T3 |
11 |
|
T25 |
11 |
| auto[1] |
auto[1] |
792 |
1 |
|
|
T24 |
11 |
|
T3 |
9 |
|
T25 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T110 |
7 |
|
T154 |
12 |
|
T196 |
8 |
| auto[1] |
83 |
1 |
|
|
T110 |
13 |
|
T154 |
8 |
|
T196 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T110 |
10 |
|
T154 |
8 |
|
T196 |
9 |
| auto[1] |
75 |
1 |
|
|
T110 |
10 |
|
T154 |
12 |
|
T196 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T110 |
13 |
|
T154 |
9 |
|
T196 |
12 |
| auto[1] |
78 |
1 |
|
|
T110 |
7 |
|
T154 |
11 |
|
T196 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T110 |
9 |
|
T154 |
11 |
|
T196 |
11 |
| auto[1] |
72 |
1 |
|
|
T110 |
11 |
|
T154 |
9 |
|
T196 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T110 |
13 |
|
T154 |
10 |
|
T196 |
7 |
| auto[1] |
82 |
1 |
|
|
T110 |
7 |
|
T154 |
10 |
|
T196 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T110 |
6 |
|
T154 |
10 |
|
T196 |
10 |
| auto[1] |
76 |
1 |
|
|
T110 |
14 |
|
T154 |
10 |
|
T196 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T110 |
12 |
|
T154 |
8 |
|
T196 |
11 |
| auto[1] |
75 |
1 |
|
|
T110 |
8 |
|
T154 |
12 |
|
T196 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T110 |
9 |
|
T154 |
8 |
|
T196 |
7 |
| auto[1] |
83 |
1 |
|
|
T110 |
11 |
|
T154 |
12 |
|
T196 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T110 |
10 |
|
T154 |
12 |
|
T196 |
11 |
| auto[1] |
82 |
1 |
|
|
T110 |
10 |
|
T154 |
8 |
|
T196 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T110 |
9 |
|
T154 |
12 |
|
T196 |
10 |
| auto[1] |
82 |
1 |
|
|
T110 |
11 |
|
T154 |
8 |
|
T196 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T110 |
10 |
|
T154 |
10 |
|
T196 |
10 |
| auto[1] |
86 |
1 |
|
|
T110 |
10 |
|
T154 |
10 |
|
T196 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T110 |
8 |
|
T154 |
11 |
|
T196 |
8 |
| auto[1] |
89 |
1 |
|
|
T110 |
12 |
|
T154 |
9 |
|
T196 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T110 |
10 |
|
T154 |
14 |
|
T196 |
12 |
| auto[1] |
71 |
1 |
|
|
T110 |
10 |
|
T154 |
6 |
|
T196 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T110 |
10 |
|
T154 |
8 |
|
T196 |
9 |
| auto[1] |
75 |
1 |
|
|
T110 |
10 |
|
T154 |
12 |
|
T196 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T110 |
14 |
|
T154 |
9 |
|
T196 |
7 |
| auto[1] |
75 |
1 |
|
|
T110 |
6 |
|
T154 |
11 |
|
T196 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T110 |
10 |
|
T154 |
13 |
|
T196 |
12 |
| auto[1] |
77 |
1 |
|
|
T110 |
10 |
|
T154 |
7 |
|
T196 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T110 |
8 |
|
T154 |
9 |
|
T196 |
9 |
| auto[1] |
83 |
1 |
|
|
T110 |
12 |
|
T154 |
11 |
|
T196 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T110 |
11 |
|
T154 |
9 |
|
T196 |
12 |
| auto[1] |
75 |
1 |
|
|
T110 |
9 |
|
T154 |
11 |
|
T196 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T110 |
9 |
|
T154 |
8 |
|
T196 |
8 |
| auto[1] |
89 |
1 |
|
|
T110 |
11 |
|
T154 |
12 |
|
T196 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T110 |
12 |
|
T154 |
10 |
|
T196 |
10 |
| auto[1] |
83 |
1 |
|
|
T110 |
8 |
|
T154 |
10 |
|
T196 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T110 |
13 |
|
T154 |
9 |
|
T196 |
9 |
| auto[1] |
83 |
1 |
|
|
T110 |
7 |
|
T154 |
11 |
|
T196 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T110 |
12 |
|
T154 |
9 |
|
T196 |
10 |
| auto[1] |
75 |
1 |
|
|
T110 |
8 |
|
T154 |
11 |
|
T196 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T110 |
11 |
|
T154 |
11 |
|
T196 |
14 |
| auto[1] |
73 |
1 |
|
|
T110 |
9 |
|
T154 |
9 |
|
T196 |
6 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T110 |
8 |
|
T154 |
11 |
|
T196 |
8 |
| auto[1] |
89 |
1 |
|
|
T110 |
12 |
|
T154 |
9 |
|
T196 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
43 |
1 |
|
|
T110 |
9 |
|
T154 |
4 |
|
T196 |
5 |
| auto[0] |
auto[1] |
42 |
1 |
|
|
T110 |
5 |
|
T154 |
5 |
|
T196 |
2 |
| auto[1] |
auto[0] |
39 |
1 |
|
|
T110 |
4 |
|
T154 |
5 |
|
T196 |
7 |
| auto[1] |
auto[1] |
36 |
1 |
|
|
T110 |
2 |
|
T154 |
6 |
|
T196 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T110 |
5 |
|
T154 |
7 |
|
T196 |
7 |
| auto[0] |
auto[1] |
38 |
1 |
|
|
T110 |
5 |
|
T154 |
6 |
|
T196 |
5 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T110 |
4 |
|
T154 |
4 |
|
T196 |
4 |
| auto[1] |
auto[1] |
34 |
1 |
|
|
T110 |
6 |
|
T154 |
3 |
|
T196 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
37 |
1 |
|
|
T110 |
5 |
|
T154 |
3 |
|
T196 |
4 |
| auto[0] |
auto[1] |
40 |
1 |
|
|
T110 |
3 |
|
T154 |
6 |
|
T196 |
5 |
| auto[1] |
auto[0] |
41 |
1 |
|
|
T110 |
8 |
|
T154 |
7 |
|
T196 |
3 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T110 |
4 |
|
T154 |
4 |
|
T196 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
44 |
1 |
|
|
T110 |
3 |
|
T154 |
3 |
|
T196 |
7 |
| auto[0] |
auto[1] |
41 |
1 |
|
|
T110 |
8 |
|
T154 |
6 |
|
T196 |
5 |
| auto[1] |
auto[0] |
40 |
1 |
|
|
T110 |
3 |
|
T154 |
7 |
|
T196 |
3 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T110 |
6 |
|
T154 |
4 |
|
T196 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
36 |
1 |
|
|
T110 |
7 |
|
T154 |
4 |
|
T196 |
3 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T110 |
2 |
|
T154 |
4 |
|
T196 |
5 |
| auto[1] |
auto[0] |
49 |
1 |
|
|
T110 |
5 |
|
T154 |
4 |
|
T196 |
8 |
| auto[1] |
auto[1] |
40 |
1 |
|
|
T110 |
6 |
|
T154 |
8 |
|
T196 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
35 |
1 |
|
|
T110 |
7 |
|
T154 |
5 |
|
T196 |
2 |
| auto[0] |
auto[1] |
42 |
1 |
|
|
T110 |
5 |
|
T154 |
5 |
|
T196 |
8 |
| auto[1] |
auto[0] |
42 |
1 |
|
|
T110 |
2 |
|
T154 |
3 |
|
T196 |
5 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T110 |
6 |
|
T154 |
7 |
|
T196 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
38 |
1 |
|
|
T110 |
3 |
|
T154 |
6 |
|
T196 |
6 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T110 |
9 |
|
T154 |
3 |
|
T196 |
4 |
| auto[1] |
auto[0] |
40 |
1 |
|
|
T110 |
6 |
|
T154 |
6 |
|
T196 |
4 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T110 |
2 |
|
T154 |
5 |
|
T196 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
37 |
1 |
|
|
T110 |
3 |
|
T154 |
6 |
|
T196 |
8 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T110 |
8 |
|
T154 |
5 |
|
T196 |
6 |
| auto[1] |
auto[0] |
37 |
1 |
|
|
T110 |
7 |
|
T154 |
4 |
|
T196 |
2 |
| auto[1] |
auto[1] |
36 |
1 |
|
|
T110 |
2 |
|
T154 |
5 |
|
T196 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T110 |
2 |
|
T154 |
8 |
|
T196 |
6 |
| auto[0] |
auto[1] |
43 |
1 |
|
|
T110 |
8 |
|
T154 |
6 |
|
T196 |
6 |
| auto[1] |
auto[0] |
31 |
1 |
|
|
T110 |
5 |
|
T154 |
4 |
|
T196 |
2 |
| auto[1] |
auto[1] |
40 |
1 |
|
|
T110 |
5 |
|
T154 |
2 |
|
T196 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
85 |
1 |
|
|
T110 |
10 |
|
T154 |
8 |
|
T196 |
9 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T110 |
10 |
|
T154 |
12 |
|
T196 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
37 |
1 |
|
|
T110 |
7 |
|
T154 |
5 |
|
T196 |
4 |
| auto[0] |
auto[1] |
40 |
1 |
|
|
T110 |
6 |
|
T154 |
4 |
|
T196 |
5 |
| auto[1] |
auto[0] |
41 |
1 |
|
|
T110 |
3 |
|
T154 |
7 |
|
T196 |
7 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T110 |
4 |
|
T154 |
4 |
|
T196 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T110 |
8 |
|
T154 |
11 |
|
T196 |
8 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T110 |
12 |
|
T154 |
9 |
|
T196 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21 |
1 |
|
|
T127 |
8 |
|
T262 |
13 |
| auto[1] |
19 |
1 |
|
|
T127 |
12 |
|
T262 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16 |
1 |
|
|
T127 |
6 |
|
T262 |
10 |
| auto[1] |
24 |
1 |
|
|
T127 |
14 |
|
T262 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21 |
1 |
|
|
T127 |
9 |
|
T262 |
12 |
| auto[1] |
19 |
1 |
|
|
T127 |
11 |
|
T262 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21 |
1 |
|
|
T127 |
13 |
|
T262 |
8 |
| auto[1] |
19 |
1 |
|
|
T127 |
7 |
|
T262 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20 |
1 |
|
|
T127 |
9 |
|
T262 |
11 |
| auto[1] |
20 |
1 |
|
|
T127 |
11 |
|
T262 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17 |
1 |
|
|
T127 |
9 |
|
T262 |
8 |
| auto[1] |
23 |
1 |
|
|
T127 |
11 |
|
T262 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18 |
1 |
|
|
T127 |
8 |
|
T262 |
10 |
| auto[1] |
22 |
1 |
|
|
T127 |
12 |
|
T262 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
22 |
1 |
|
|
T127 |
11 |
|
T262 |
11 |
| auto[1] |
18 |
1 |
|
|
T127 |
9 |
|
T262 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21 |
1 |
|
|
T127 |
9 |
|
T262 |
12 |
| auto[1] |
19 |
1 |
|
|
T127 |
11 |
|
T262 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18 |
1 |
|
|
T127 |
8 |
|
T262 |
10 |
| auto[1] |
22 |
1 |
|
|
T127 |
12 |
|
T262 |
10 |