Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T25 |
13 |
|
T26 |
13 |
|
T8 |
12 |
| auto[1] |
861 |
1 |
|
|
T25 |
7 |
|
T26 |
7 |
|
T8 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T25 |
10 |
|
T26 |
14 |
|
T8 |
9 |
| auto[1] |
865 |
1 |
|
|
T25 |
10 |
|
T26 |
6 |
|
T8 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T25 |
9 |
|
T26 |
9 |
|
T8 |
12 |
| auto[1] |
841 |
1 |
|
|
T25 |
11 |
|
T26 |
11 |
|
T8 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T25 |
10 |
|
T26 |
13 |
|
T8 |
11 |
| auto[1] |
856 |
1 |
|
|
T25 |
10 |
|
T26 |
7 |
|
T8 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T25 |
12 |
|
T26 |
9 |
|
T8 |
11 |
| auto[1] |
891 |
1 |
|
|
T25 |
8 |
|
T26 |
11 |
|
T8 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T25 |
10 |
|
T26 |
11 |
|
T8 |
10 |
| auto[1] |
862 |
1 |
|
|
T25 |
10 |
|
T26 |
9 |
|
T8 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T25 |
9 |
|
T26 |
12 |
|
T8 |
15 |
| auto[1] |
860 |
1 |
|
|
T25 |
11 |
|
T26 |
8 |
|
T8 |
5 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T25 |
11 |
|
T26 |
12 |
|
T8 |
10 |
| auto[1] |
866 |
1 |
|
|
T25 |
9 |
|
T26 |
8 |
|
T8 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T25 |
13 |
|
T26 |
9 |
|
T8 |
11 |
| auto[1] |
849 |
1 |
|
|
T25 |
7 |
|
T26 |
11 |
|
T8 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T25 |
7 |
|
T26 |
9 |
|
T8 |
12 |
| auto[1] |
886 |
1 |
|
|
T25 |
13 |
|
T26 |
11 |
|
T8 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T25 |
8 |
|
T26 |
10 |
|
T8 |
9 |
| auto[1] |
880 |
1 |
|
|
T25 |
12 |
|
T26 |
10 |
|
T8 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T25 |
7 |
|
T26 |
6 |
|
T8 |
6 |
| auto[1] |
877 |
1 |
|
|
T25 |
13 |
|
T26 |
14 |
|
T8 |
14 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T25 |
13 |
|
T26 |
11 |
|
T8 |
14 |
| auto[1] |
860 |
1 |
|
|
T25 |
7 |
|
T26 |
9 |
|
T8 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T25 |
10 |
|
T26 |
14 |
|
T8 |
9 |
| auto[1] |
865 |
1 |
|
|
T25 |
10 |
|
T26 |
6 |
|
T8 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
857 |
1 |
|
|
T25 |
11 |
|
T26 |
13 |
|
T8 |
8 |
| auto[1] |
863 |
1 |
|
|
T25 |
9 |
|
T26 |
7 |
|
T8 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T25 |
12 |
|
T26 |
11 |
|
T8 |
13 |
| auto[1] |
830 |
1 |
|
|
T25 |
8 |
|
T26 |
9 |
|
T8 |
7 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
870 |
1 |
|
|
T25 |
13 |
|
T26 |
8 |
|
T8 |
12 |
| auto[1] |
850 |
1 |
|
|
T25 |
7 |
|
T26 |
12 |
|
T8 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
837 |
1 |
|
|
T25 |
11 |
|
T26 |
8 |
|
T8 |
9 |
| auto[1] |
883 |
1 |
|
|
T25 |
9 |
|
T26 |
12 |
|
T8 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T25 |
14 |
|
T26 |
13 |
|
T8 |
13 |
| auto[1] |
888 |
1 |
|
|
T25 |
6 |
|
T26 |
7 |
|
T8 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T25 |
12 |
|
T26 |
13 |
|
T8 |
10 |
| auto[1] |
852 |
1 |
|
|
T25 |
8 |
|
T26 |
7 |
|
T8 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T25 |
11 |
|
T26 |
6 |
|
T8 |
8 |
| auto[1] |
899 |
1 |
|
|
T25 |
9 |
|
T26 |
14 |
|
T8 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T25 |
13 |
|
T26 |
9 |
|
T8 |
8 |
| auto[1] |
881 |
1 |
|
|
T25 |
7 |
|
T26 |
11 |
|
T8 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T25 |
12 |
|
T26 |
10 |
|
T8 |
11 |
| auto[1] |
855 |
1 |
|
|
T25 |
8 |
|
T26 |
10 |
|
T8 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T25 |
7 |
|
T26 |
6 |
|
T8 |
6 |
| auto[1] |
877 |
1 |
|
|
T25 |
13 |
|
T26 |
14 |
|
T8 |
14 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T25 |
5 |
|
T26 |
5 |
|
T8 |
6 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T25 |
6 |
|
T26 |
8 |
|
T8 |
2 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T25 |
4 |
|
T26 |
4 |
|
T8 |
6 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T25 |
5 |
|
T26 |
3 |
|
T8 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
443 |
1 |
|
|
T25 |
6 |
|
T26 |
6 |
|
T8 |
8 |
| auto[0] |
auto[1] |
447 |
1 |
|
|
T25 |
6 |
|
T26 |
5 |
|
T8 |
5 |
| auto[1] |
auto[0] |
421 |
1 |
|
|
T25 |
4 |
|
T26 |
7 |
|
T8 |
3 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T25 |
4 |
|
T26 |
2 |
|
T8 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T25 |
8 |
|
T26 |
2 |
|
T8 |
8 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T25 |
5 |
|
T26 |
6 |
|
T8 |
4 |
| auto[1] |
auto[0] |
395 |
1 |
|
|
T25 |
4 |
|
T26 |
7 |
|
T8 |
3 |
| auto[1] |
auto[1] |
455 |
1 |
|
|
T25 |
3 |
|
T26 |
5 |
|
T8 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
432 |
1 |
|
|
T25 |
6 |
|
T26 |
3 |
|
T8 |
6 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T25 |
5 |
|
T26 |
5 |
|
T8 |
3 |
| auto[1] |
auto[0] |
426 |
1 |
|
|
T25 |
4 |
|
T26 |
8 |
|
T8 |
4 |
| auto[1] |
auto[1] |
457 |
1 |
|
|
T25 |
5 |
|
T26 |
4 |
|
T8 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T25 |
7 |
|
T26 |
8 |
|
T8 |
11 |
| auto[0] |
auto[1] |
406 |
1 |
|
|
T25 |
7 |
|
T26 |
5 |
|
T8 |
2 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T25 |
2 |
|
T26 |
4 |
|
T8 |
4 |
| auto[1] |
auto[1] |
454 |
1 |
|
|
T25 |
4 |
|
T26 |
3 |
|
T8 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T25 |
7 |
|
T26 |
8 |
|
T8 |
7 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T25 |
5 |
|
T26 |
5 |
|
T8 |
3 |
| auto[1] |
auto[0] |
413 |
1 |
|
|
T25 |
4 |
|
T26 |
4 |
|
T8 |
3 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T25 |
4 |
|
T26 |
3 |
|
T8 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
403 |
1 |
|
|
T25 |
5 |
|
T26 |
5 |
|
T8 |
4 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T25 |
8 |
|
T26 |
4 |
|
T8 |
4 |
| auto[1] |
auto[0] |
431 |
1 |
|
|
T25 |
2 |
|
T26 |
4 |
|
T8 |
8 |
| auto[1] |
auto[1] |
450 |
1 |
|
|
T25 |
5 |
|
T26 |
7 |
|
T8 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T25 |
5 |
|
T26 |
6 |
|
T8 |
4 |
| auto[0] |
auto[1] |
446 |
1 |
|
|
T25 |
7 |
|
T26 |
4 |
|
T8 |
7 |
| auto[1] |
auto[0] |
421 |
1 |
|
|
T25 |
3 |
|
T26 |
4 |
|
T8 |
5 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T25 |
5 |
|
T26 |
6 |
|
T8 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
440 |
1 |
|
|
T25 |
8 |
|
T26 |
6 |
|
T8 |
10 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T25 |
5 |
|
T26 |
5 |
|
T8 |
4 |
| auto[1] |
auto[0] |
419 |
1 |
|
|
T25 |
5 |
|
T26 |
7 |
|
T8 |
2 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T25 |
2 |
|
T26 |
2 |
|
T8 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
855 |
1 |
|
|
T25 |
10 |
|
T26 |
14 |
|
T8 |
9 |
| auto[1] |
auto[1] |
865 |
1 |
|
|
T25 |
10 |
|
T26 |
6 |
|
T8 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
420 |
1 |
|
|
T25 |
7 |
|
T26 |
3 |
|
T8 |
4 |
| auto[0] |
auto[1] |
401 |
1 |
|
|
T25 |
4 |
|
T26 |
3 |
|
T8 |
4 |
| auto[1] |
auto[0] |
451 |
1 |
|
|
T25 |
6 |
|
T26 |
6 |
|
T8 |
7 |
| auto[1] |
auto[1] |
448 |
1 |
|
|
T25 |
3 |
|
T26 |
8 |
|
T8 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
843 |
1 |
|
|
T25 |
7 |
|
T26 |
6 |
|
T8 |
6 |
| auto[1] |
auto[1] |
877 |
1 |
|
|
T25 |
13 |
|
T26 |
14 |
|
T8 |
14 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
198 |
1 |
|
|
T8 |
11 |
|
T36 |
12 |
|
T165 |
9 |
| auto[1] |
182 |
1 |
|
|
T8 |
9 |
|
T36 |
8 |
|
T165 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T8 |
10 |
|
T36 |
11 |
|
T165 |
11 |
| auto[1] |
190 |
1 |
|
|
T8 |
10 |
|
T36 |
9 |
|
T165 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
197 |
1 |
|
|
T8 |
11 |
|
T36 |
8 |
|
T165 |
12 |
| auto[1] |
183 |
1 |
|
|
T8 |
9 |
|
T36 |
12 |
|
T165 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
204 |
1 |
|
|
T8 |
14 |
|
T36 |
7 |
|
T165 |
5 |
| auto[1] |
176 |
1 |
|
|
T8 |
6 |
|
T36 |
13 |
|
T165 |
15 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
192 |
1 |
|
|
T8 |
12 |
|
T36 |
10 |
|
T165 |
12 |
| auto[1] |
188 |
1 |
|
|
T8 |
8 |
|
T36 |
10 |
|
T165 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T8 |
9 |
|
T36 |
10 |
|
T165 |
9 |
| auto[1] |
197 |
1 |
|
|
T8 |
11 |
|
T36 |
10 |
|
T165 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
176 |
1 |
|
|
T8 |
11 |
|
T36 |
10 |
|
T165 |
8 |
| auto[1] |
204 |
1 |
|
|
T8 |
9 |
|
T36 |
10 |
|
T165 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
196 |
1 |
|
|
T8 |
11 |
|
T36 |
7 |
|
T165 |
13 |
| auto[1] |
184 |
1 |
|
|
T8 |
9 |
|
T36 |
13 |
|
T165 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T8 |
10 |
|
T36 |
9 |
|
T165 |
6 |
| auto[1] |
203 |
1 |
|
|
T8 |
10 |
|
T36 |
11 |
|
T165 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T8 |
9 |
|
T36 |
11 |
|
T165 |
8 |
| auto[1] |
186 |
1 |
|
|
T8 |
11 |
|
T36 |
9 |
|
T165 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
206 |
1 |
|
|
T8 |
11 |
|
T36 |
12 |
|
T165 |
11 |
| auto[1] |
174 |
1 |
|
|
T8 |
9 |
|
T36 |
8 |
|
T165 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
184 |
1 |
|
|
T8 |
9 |
|
T36 |
6 |
|
T165 |
9 |
| auto[1] |
196 |
1 |
|
|
T8 |
11 |
|
T36 |
14 |
|
T165 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T8 |
11 |
|
T36 |
9 |
|
T165 |
13 |
| auto[1] |
186 |
1 |
|
|
T8 |
9 |
|
T36 |
11 |
|
T165 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T8 |
10 |
|
T36 |
11 |
|
T165 |
11 |
| auto[1] |
190 |
1 |
|
|
T8 |
10 |
|
T36 |
9 |
|
T165 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
196 |
1 |
|
|
T8 |
7 |
|
T36 |
10 |
|
T165 |
6 |
| auto[1] |
184 |
1 |
|
|
T8 |
13 |
|
T36 |
10 |
|
T165 |
14 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T8 |
8 |
|
T36 |
11 |
|
T165 |
11 |
| auto[1] |
199 |
1 |
|
|
T8 |
12 |
|
T36 |
9 |
|
T165 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
180 |
1 |
|
|
T8 |
12 |
|
T36 |
11 |
|
T165 |
6 |
| auto[1] |
200 |
1 |
|
|
T8 |
8 |
|
T36 |
9 |
|
T165 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
193 |
1 |
|
|
T8 |
9 |
|
T36 |
11 |
|
T165 |
9 |
| auto[1] |
187 |
1 |
|
|
T8 |
11 |
|
T36 |
9 |
|
T165 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
187 |
1 |
|
|
T8 |
12 |
|
T36 |
11 |
|
T165 |
10 |
| auto[1] |
193 |
1 |
|
|
T8 |
8 |
|
T36 |
9 |
|
T165 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T8 |
10 |
|
T36 |
8 |
|
T165 |
11 |
| auto[1] |
209 |
1 |
|
|
T8 |
10 |
|
T36 |
12 |
|
T165 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
193 |
1 |
|
|
T8 |
9 |
|
T36 |
13 |
|
T165 |
11 |
| auto[1] |
187 |
1 |
|
|
T8 |
11 |
|
T36 |
7 |
|
T165 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T8 |
12 |
|
T36 |
13 |
|
T165 |
9 |
| auto[1] |
178 |
1 |
|
|
T8 |
8 |
|
T36 |
7 |
|
T165 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T8 |
8 |
|
T36 |
12 |
|
T165 |
10 |
| auto[1] |
190 |
1 |
|
|
T8 |
12 |
|
T36 |
8 |
|
T165 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
184 |
1 |
|
|
T8 |
9 |
|
T36 |
6 |
|
T165 |
9 |
| auto[1] |
196 |
1 |
|
|
T8 |
11 |
|
T36 |
14 |
|
T165 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
97 |
1 |
|
|
T8 |
3 |
|
T36 |
5 |
|
T165 |
3 |
| auto[0] |
auto[1] |
99 |
1 |
|
|
T8 |
4 |
|
T36 |
5 |
|
T165 |
3 |
| auto[1] |
auto[0] |
100 |
1 |
|
|
T8 |
8 |
|
T36 |
3 |
|
T165 |
9 |
| auto[1] |
auto[1] |
84 |
1 |
|
|
T8 |
5 |
|
T36 |
7 |
|
T165 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
93 |
1 |
|
|
T8 |
5 |
|
T36 |
5 |
|
T165 |
2 |
| auto[0] |
auto[1] |
88 |
1 |
|
|
T8 |
3 |
|
T36 |
6 |
|
T165 |
9 |
| auto[1] |
auto[0] |
111 |
1 |
|
|
T8 |
9 |
|
T36 |
2 |
|
T165 |
3 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T8 |
3 |
|
T36 |
7 |
|
T165 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
87 |
1 |
|
|
T8 |
7 |
|
T36 |
4 |
|
T165 |
3 |
| auto[0] |
auto[1] |
93 |
1 |
|
|
T8 |
5 |
|
T36 |
7 |
|
T165 |
3 |
| auto[1] |
auto[0] |
105 |
1 |
|
|
T8 |
5 |
|
T36 |
6 |
|
T165 |
9 |
| auto[1] |
auto[1] |
95 |
1 |
|
|
T8 |
3 |
|
T36 |
3 |
|
T165 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
89 |
1 |
|
|
T8 |
4 |
|
T36 |
4 |
|
T165 |
3 |
| auto[0] |
auto[1] |
104 |
1 |
|
|
T8 |
5 |
|
T36 |
7 |
|
T165 |
6 |
| auto[1] |
auto[0] |
94 |
1 |
|
|
T8 |
5 |
|
T36 |
6 |
|
T165 |
6 |
| auto[1] |
auto[1] |
93 |
1 |
|
|
T8 |
6 |
|
T36 |
3 |
|
T165 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
82 |
1 |
|
|
T8 |
8 |
|
T36 |
6 |
|
T165 |
2 |
| auto[0] |
auto[1] |
105 |
1 |
|
|
T8 |
4 |
|
T36 |
5 |
|
T165 |
8 |
| auto[1] |
auto[0] |
94 |
1 |
|
|
T8 |
3 |
|
T36 |
4 |
|
T165 |
6 |
| auto[1] |
auto[1] |
99 |
1 |
|
|
T8 |
5 |
|
T36 |
5 |
|
T165 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T8 |
7 |
|
T36 |
3 |
|
T165 |
5 |
| auto[0] |
auto[1] |
87 |
1 |
|
|
T8 |
3 |
|
T36 |
5 |
|
T165 |
6 |
| auto[1] |
auto[0] |
112 |
1 |
|
|
T8 |
4 |
|
T36 |
4 |
|
T165 |
8 |
| auto[1] |
auto[1] |
97 |
1 |
|
|
T8 |
6 |
|
T36 |
8 |
|
T165 |
1 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
96 |
1 |
|
|
T8 |
5 |
|
T36 |
6 |
|
T165 |
4 |
| auto[0] |
auto[1] |
106 |
1 |
|
|
T8 |
7 |
|
T36 |
7 |
|
T165 |
5 |
| auto[1] |
auto[0] |
98 |
1 |
|
|
T8 |
4 |
|
T36 |
5 |
|
T165 |
4 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T8 |
4 |
|
T36 |
2 |
|
T165 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
96 |
1 |
|
|
T8 |
4 |
|
T36 |
6 |
|
T165 |
6 |
| auto[0] |
auto[1] |
94 |
1 |
|
|
T8 |
4 |
|
T36 |
6 |
|
T165 |
4 |
| auto[1] |
auto[0] |
110 |
1 |
|
|
T8 |
7 |
|
T36 |
6 |
|
T165 |
5 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T8 |
5 |
|
T36 |
2 |
|
T165 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
102 |
1 |
|
|
T8 |
6 |
|
T36 |
5 |
|
T165 |
6 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T8 |
5 |
|
T36 |
4 |
|
T165 |
7 |
| auto[1] |
auto[0] |
96 |
1 |
|
|
T8 |
5 |
|
T36 |
7 |
|
T165 |
3 |
| auto[1] |
auto[1] |
90 |
1 |
|
|
T8 |
4 |
|
T36 |
4 |
|
T165 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
190 |
1 |
|
|
T8 |
10 |
|
T36 |
11 |
|
T165 |
11 |
| auto[1] |
auto[1] |
190 |
1 |
|
|
T8 |
10 |
|
T36 |
9 |
|
T165 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T8 |
3 |
|
T36 |
6 |
|
T165 |
3 |
| auto[0] |
auto[1] |
107 |
1 |
|
|
T8 |
6 |
|
T36 |
7 |
|
T165 |
8 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T8 |
7 |
|
T36 |
3 |
|
T165 |
3 |
| auto[1] |
auto[1] |
96 |
1 |
|
|
T8 |
4 |
|
T36 |
4 |
|
T165 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
184 |
1 |
|
|
T8 |
9 |
|
T36 |
6 |
|
T165 |
9 |
| auto[1] |
auto[1] |
196 |
1 |
|
|
T8 |
11 |
|
T36 |
14 |
|
T165 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T8 |
8 |
|
T40 |
11 |
|
T93 |
11 |
| auto[1] |
70 |
1 |
|
|
T8 |
12 |
|
T40 |
9 |
|
T93 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T8 |
11 |
|
T40 |
14 |
|
T93 |
8 |
| auto[1] |
70 |
1 |
|
|
T8 |
9 |
|
T40 |
6 |
|
T93 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T8 |
10 |
|
T40 |
9 |
|
T93 |
9 |
| auto[1] |
69 |
1 |
|
|
T8 |
10 |
|
T40 |
11 |
|
T93 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T8 |
13 |
|
T40 |
12 |
|
T93 |
12 |
| auto[1] |
63 |
1 |
|
|
T8 |
7 |
|
T40 |
8 |
|
T93 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T8 |
12 |
|
T40 |
9 |
|
T93 |
10 |
| auto[1] |
66 |
1 |
|
|
T8 |
8 |
|
T40 |
11 |
|
T93 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T8 |
8 |
|
T40 |
14 |
|
T93 |
12 |
| auto[1] |
70 |
1 |
|
|
T8 |
12 |
|
T40 |
6 |
|
T93 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T8 |
8 |
|
T40 |
10 |
|
T93 |
13 |
| auto[1] |
72 |
1 |
|
|
T8 |
12 |
|
T40 |
10 |
|
T93 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T8 |
13 |
|
T40 |
6 |
|
T93 |
11 |
| auto[1] |
69 |
1 |
|
|
T8 |
7 |
|
T40 |
14 |
|
T93 |
9 |