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Summary for Variable cfg.vif.ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 17 1 T8 8 T110 9
auto[1] 23 1 T8 12 T110 11



Summary for Variable cfg.vif.bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.bat_disable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 18 1 T8 10 T110 8
auto[1] 22 1 T8 10 T110 12



Summary for Variable cfg.vif.key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 16 1 T8 8 T110 8
auto[1] 24 1 T8 12 T110 12



Summary for Variable cfg.vif.key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key0_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 20 1 T8 13 T110 7
auto[1] 20 1 T8 7 T110 13



Summary for Variable cfg.vif.key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 20 1 T8 9 T110 11
auto[1] 20 1 T8 11 T110 9



Summary for Variable cfg.vif.key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 17 1 T8 8 T110 9
auto[1] 23 1 T8 12 T110 11



Summary for Variable cfg.vif.key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 16 1 T8 9 T110 7
auto[1] 24 1 T8 11 T110 13



Summary for Variable cfg.vif.key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 22 1 T8 9 T110 13
auto[1] 18 1 T8 11 T110 7



Summary for Variable cfg.vif.lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 16 1 T8 7 T110 9
auto[1] 24 1 T8 13 T110 11



Summary for Variable cfg.vif.pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 22 1 T8 12 T110 10
auto[1] 18 1 T8 8 T110 10



Summary for Variable cfg.vif.pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 19 1 T8 9 T110 10
auto[1] 21 1 T8 11 T110 10



Summary for Variable cfg.vif.z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 22 1 T8 13 T110 9
auto[1] 18 1 T8 7 T110 11



Summary for Variable cp_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 18 1 T8 6 T110 12
auto[1] 22 1 T8 14 T110 8



Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 18 1 T8 10 T110 8
auto[1] 22 1 T8 10 T110 12



Summary for Variable cp_key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 15 1 T8 5 T110 10
auto[1] 25 1 T8 15 T110 10



Summary for Variable cp_key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 17 1 T8 6 T110 11
auto[1] 23 1 T8 14 T110 9



Summary for Variable cp_key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 21 1 T8 13 T110 8
auto[1] 19 1 T8 7 T110 12



Summary for Variable cp_key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 22 1 T8 10 T110 12
auto[1] 18 1 T8 10 T110 8



Summary for Variable cp_key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 21 1 T8 11 T110 10
auto[1] 19 1 T8 9 T110 10



Summary for Variable cp_key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 15 1 T8 9 T110 6
auto[1] 25 1 T8 11 T110 14



Summary for Variable cp_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 25 1 T8 15 T110 10
auto[1] 15 1 T8 5 T110 10



Summary for Variable cp_pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 22 1 T8 10 T110 12
auto[1] 18 1 T8 10 T110 8



Summary for Variable cp_pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 23 1 T8 11 T110 12
auto[1] 17 1 T8 9 T110 8



Summary for Variable cp_z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 22 1 T8 13 T110 9
auto[1] 18 1 T8 7 T110 11



Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_inXval

Bins
cp_key0_incfg.vif.key0_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 4 1 T8 1 T110 3
auto[0] auto[1] 11 1 T8 4 T110 7
auto[1] auto[0] 12 1 T8 7 T110 5
auto[1] auto[1] 13 1 T8 8 T110 5



Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_outXval

Bins
cp_key0_outcfg.vif.key0_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 7 1 T8 4 T110 3
auto[0] auto[1] 10 1 T8 2 T110 8
auto[1] auto[0] 13 1 T8 9 T110 4
auto[1] auto[1] 10 1 T8 5 T110 5



Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_inXval

Bins
cp_key1_incfg.vif.key1_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 9 1 T8 5 T110 4
auto[0] auto[1] 12 1 T8 8 T110 4
auto[1] auto[0] 11 1 T8 4 T110 7
auto[1] auto[1] 8 1 T8 3 T110 5



Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_outXval

Bins
cp_key1_outcfg.vif.key1_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 8 1 T8 3 T110 5
auto[0] auto[1] 14 1 T8 7 T110 7
auto[1] auto[0] 9 1 T8 5 T110 4
auto[1] auto[1] 9 1 T8 5 T110 4



Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_incfg.vif.key2_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 8 1 T8 6 T110 2
auto[0] auto[1] 13 1 T8 5 T110 8
auto[1] auto[0] 8 1 T8 3 T110 5
auto[1] auto[1] 11 1 T8 6 T110 5



Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 8 1 T8 5 T110 3
auto[0] auto[1] 7 1 T8 4 T110 3
auto[1] auto[0] 14 1 T8 4 T110 10
auto[1] auto[1] 11 1 T8 7 T110 4



Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 11 1 T8 5 T110 6
auto[0] auto[1] 11 1 T8 5 T110 6
auto[1] auto[0] 11 1 T8 7 T110 4
auto[1] auto[1] 7 1 T8 3 T110 4



Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 10 1 T8 4 T110 6
auto[0] auto[1] 13 1 T8 7 T110 6
auto[1] auto[0] 9 1 T8 5 T110 4
auto[1] auto[1] 8 1 T8 4 T110 4



Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 8 1 T8 2 T110 6
auto[0] auto[1] 10 1 T8 4 T110 6
auto[1] auto[0] 9 1 T8 6 T110 3
auto[1] auto[1] 13 1 T8 8 T110 5



Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 18 1 T8 10 T110 8
auto[1] auto[1] 22 1 T8 10 T110 12


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded



Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 12 1 T8 6 T110 6
auto[0] auto[1] 13 1 T8 9 T110 4
auto[1] auto[0] 4 1 T8 1 T110 3
auto[1] auto[1] 11 1 T8 4 T110 7



Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 22 1 T8 13 T110 9
auto[1] auto[1] 18 1 T8 7 T110 11


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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