Unified Coverage Report :: Group Instance : sysrst_ctrl_key_invert_ctl_cg_(2)

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

786

1

T17

10

T27

10

T28

6

auto[1]

805

1

T17

10

T27

10

T28

14

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

770

1

T17

12

T27

7

T28

13

auto[1]

821

1

T17

8

T27

13

T28

7

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844

1

T17

16

T27

7

T28

13

auto[1]

747

1

T17

4

T27

13

T28

7

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

817

1

T17

13

T27

9

T28

12

auto[1]

774

1

T17

7

T27

11

T28

8

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

789

1

T17

11

T27

10

T28

12

auto[1]

802

1

T17

9

T27

10

T28

8

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

778

1

T17

11

T27

10

T28

7

auto[1]

813

1

T17

9

T27

10

T28

13

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

801

1

T17

13

T27

10

T28

13

auto[1]

790

1

T17

7

T27

10

T28

7

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

779

1

T17

8

T27

11

T28

11

auto[1]

812

1

T17

12

T27

9

T28

9

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

832

1

T17

14

T27

10

T28

7

auto[1]

759

1

T17

6

T27

10

T28

13

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

795

1

T17

8

T27

10

T28

8

auto[1]

796

1

T17

12

T27

10

T28

12

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

782

1

T17

11

T27

14

T28

9

auto[1]

809

1

T17

9

T27

6

T28

11

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

764

1

T17

10

T27

6

T28

8

auto[1]

827

1

T17

10

T27

14

T28

12

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

813

1

T17

13

T27

7

T28

10

auto[1]

778

1

T17

7

T27

13

T28

10

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

769

1

T17

12

T27

7

T28

13

auto[1]

822

1

T17

8

T27

13

T28

7

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

795

1

T17

8

T27

4

T28

7

auto[1]

796

1

T17

12

T27

16

T28

13

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

762

1

T17

9

T27

12

T28

10

auto[1]

829

1

T17

11

T27

8

T28

10

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

779

1

T17

8

T27

13

T28

7

auto[1]

812

1

T17

12

T27

7

T28

13

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

820

1

T17

10

T27

13

T28

8

auto[1]

771

1

T17

10

T27

7

T28

12

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

798

1

T17

13

T27

9

T28

13

auto[1]

793

1

T17

7

T27

11

T28

7

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

806

1

T17

12

T27

6

T28

9

auto[1]

785

1

T17

8

T27

14

T28

11

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814

1

T17

15

T27

5

T28

9

auto[1]

777

1

T17

5

T27

15

T28

11

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

796

1

T17

11

T27

11

T28

10

auto[1]

795

1

T17

9

T27

9

T28

10

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

791

1

T17

10

T27

11

T28

11

auto[1]

800

1

T17

10

T27

9

T28

9

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

764

1

T17

10

T27

6

T28

8

auto[1]

827

1

T17

10

T27

14

T28

12

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

415

1

T17

5

T27

2

T28

4

auto[0]

auto[1]

380

1

T17

3

T27

2

T28

3

auto[1]

auto[0]

429

1

T17

11

T27

5

T28

9

auto[1]

auto[1]

367

1

T17

1

T27

11

T28

4

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

385

1

T17

4

T27

7

T28

5

auto[0]

auto[1]

377

1

T17

5

T27

5

T28

5

auto[1]

auto[0]

432

1

T17

9

T27

2

T28

7

auto[1]

auto[1]

397

1

T17

2

T27

6

T28

3

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

379

1

T17

4

T27

4

T28

6

auto[0]

auto[1]

400

1

T17

4

T27

9

T28

1

auto[1]

auto[0]

410

1

T17

7

T27

6

T28

6

auto[1]

auto[1]

402

1

T17

5

T27

1

T28

7

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

394

1

T17

5

T27

4

T28

4

auto[0]

auto[1]

426

1

T17

5

T27

9

T28

4

auto[1]

auto[0]

384

1

T17

6

T27

6

T28

3

auto[1]

auto[1]

387

1

T17

4

T27

1

T28

9

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

410

1

T17

10

T27

5

T28

10

auto[0]

auto[1]

388

1

T17

3

T27

4

T28

3

auto[1]

auto[0]

391

1

T17

3

T27

5

T28

3

auto[1]

auto[1]

402

1

T17

4

T27

6

T28

4

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

403

1

T17

7

T27

4

T28

7

auto[0]

auto[1]

403

1

T17

5

T27

2

T28

2

auto[1]

auto[0]

376

1

T17

1

T27

7

T28

4

auto[1]

auto[1]

409

1

T17

7

T27

7

T28

7

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

397

1

T17

5

T27

8

T28

4

auto[0]

auto[1]

399

1

T17

6

T27

3

T28

6

auto[1]

auto[0]

398

1

T17

3

T27

2

T28

4

auto[1]

auto[1]

397

1

T17

6

T27

7

T28

6

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

388

1

T17

6

T27

10

T28

5

auto[0]

auto[1]

403

1

T17

4

T27

1

T28

6

auto[1]

auto[0]

394

1

T17

5

T27

4

T28

4

auto[1]

auto[1]

406

1

T17

5

T27

5

T28

5

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

421

1

T17

6

T27

3

T28

2

auto[0]

auto[1]

392

1

T17

7

T27

4

T28

8

auto[1]

auto[0]

365

1

T17

4

T27

7

T28

4

auto[1]

auto[1]

413

1

T17

3

T27

6

T28

6

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

769

1

T17

12

T27

7

T28

13

auto[1]

auto[1]

821

1

T17

8

T27

13

T28

7

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

435

1

T17

12

T27

3

T28

3

auto[0]

auto[1]

379

1

T17

3

T27

2

T28

6

auto[1]

auto[0]

397

1

T17

2

T27

7

T28

4

auto[1]

auto[1]

380

1

T17

3

T27

8

T28

7

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

764

1

T17

10

T27

6

T28

8

auto[1]

auto[1]

827

1

T17

10

T27

14

T28

12

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131

1

T68

8

T71

10

T85

8

auto[1]

149

1

T68

12

T71

10

T85

12

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123

1

T68

10

T71

7

T85

5

auto[1]

157

1

T68

10

T71

13

T85

15

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140

1

T68

13

T71

9

T85

10

auto[1]

140

1

T68

7

T71

11

T85

10

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137

1

T68

12

T71

11

T85

11

auto[1]

143

1

T68

8

T71

9

T85

9

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138

1

T68

10

T71

10

T85

11

auto[1]

142

1

T68

10

T71

10

T85

9

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146

1

T68

8

T71

11

T85

10

auto[1]

134

1

T68

12

T71

9

T85

10

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141

1

T68

9

T71

8

T85

7

auto[1]

139

1

T68

11

T71

12

T85

13

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130

1

T68

10

T71

9

T85

10

auto[1]

150

1

T68

10

T71

11

T85

10

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145

1

T68

10

T71

14

T85

10

auto[1]

135

1

T68

10

T71

6

T85

10

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151

1

T68

12

T71

12

T85

10

auto[1]

129

1

T68

8

T71

8

T85

10

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148

1

T68

11

T71

8

T85

12

auto[1]

132

1

T68

9

T71

12

T85

8

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139

1

T68

9

T71

14

T85

9

auto[1]

141

1

T68

11

T71

6

T85

11

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149

1

T68

13

T71

10

T85

9

auto[1]

131

1

T68

7

T71

10

T85

11

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123

1

T68

10

T71

7

T85

5

auto[1]

157

1

T68

10

T71

13

T85

15

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152

1

T68

8

T71

14

T85

13

auto[1]

128

1

T68

12

T71

6

T85

7

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135

1

T68

11

T71

8

T85

10

auto[1]

145

1

T68

9

T71

12

T85

10

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126

1

T68

8

T71

9

T85

10

auto[1]

154

1

T68

12

T71

11

T85

10

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144

1

T68

14

T71

12

T85

7

auto[1]

136

1

T68

6

T71

8

T85

13

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133

1

T68

10

T71

8

T85

9

auto[1]

147

1

T68

10

T71

12

T85

11

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146

1

T68

11

T71

13

T85

10

auto[1]

134

1

T68

9

T71

7

T85

10

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136

1

T68

10

T71

7

T85

9

auto[1]

144

1

T68

10

T71

13

T85

11

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131

1

T68

8

T71

7

T85

12

auto[1]

149

1

T68

12

T71

13

T85

8

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136

1

T68

7

T71

7

T85

12

auto[1]

144

1

T68

13

T71

13

T85

8

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139

1

T68

9

T71

14

T85

9

auto[1]

141

1

T68

11

T71

6

T85

11

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

79

1

T68

5

T71

7

T85

8

auto[0]

auto[1]

73

1

T68

3

T71

7

T85

5

auto[1]

auto[0]

61

1

T68

8

T71

2

T85

2

auto[1]

auto[1]

67

1

T68

4

T71

4

T85

5

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

69

1

T68

6

T71

5

T85

7

auto[0]

auto[1]

66

1

T68

5

T71

3

T85

3

auto[1]

auto[0]

68

1

T68

6

T71

6

T85

4

auto[1]

auto[1]

77

1

T68

3

T71

6

T85

6

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

61

1

T68

4

T71

6

T85

6

auto[0]

auto[1]

65

1

T68

4

T71

3

T85

4

auto[1]

auto[0]

77

1

T68

6

T71

4

T85

5

auto[1]

auto[1]

77

1

T68

6

T71

7

T85

5

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

74

1

T68

6

T71

8

T85

4

auto[0]

auto[1]

70

1

T68

8

T71

4

T85

3

auto[1]

auto[0]

72

1

T68

2

T71

3

T85

6

auto[1]

auto[1]

64

1

T68

4

T71

5

T85

7

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

64

1

T68

5

T71

3

T85

3

auto[0]

auto[1]

69

1

T68

5

T71

5

T85

6

auto[1]

auto[0]

77

1

T68

4

T71

5

T85

4

auto[1]

auto[1]

70

1

T68

6

T71

7

T85

7

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

65

1

T68

6

T71

6

T85

5

auto[0]

auto[1]

81

1

T68

5

T71

7

T85

5

auto[1]

auto[0]

65

1

T68

4

T71

3

T85

5

auto[1]

auto[1]

69

1

T68

5

T71

4

T85

5

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

74

1

T68

6

T71

5

T85

6

auto[0]

auto[1]

57

1

T68

2

T71

2

T85

6

auto[1]

auto[0]

77

1

T68

6

T71

7

T85

4

auto[1]

auto[1]

72

1

T68

6

T71

6

T85

4

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

75

1

T68

5

T71

3

T85

7

auto[0]

auto[1]

61

1

T68

2

T71

4

T85

5

auto[1]

auto[0]

73

1

T68

6

T71

5

T85

5

auto[1]

auto[1]

71

1

T68

7

T71

8

T85

3

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

69

1

T68

4

T71

5

T85

5

auto[0]

auto[1]

80

1

T68

9

T71

5

T85

4

auto[1]

auto[0]

62

1

T68

4

T71

5

T85

3

auto[1]

auto[1]

69

1

T68

3

T71

5

T85

8

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

123

1

T68

10

T71

7

T85

5

auto[1]

auto[1]

157

1

T68

10

T71

13

T85

15

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

73

1

T68

5

T71

4

T85

5

auto[0]

auto[1]

63

1

T68

5

T71

3

T85

4

auto[1]

auto[0]

72

1

T68

5

T71

10

T85

5

auto[1]

auto[1]

72

1

T68

5

T71

3

T85

6

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

139

1

T68

9

T71

14

T85

9

auto[1]

auto[1]

141

1

T68

11

T71

6

T85

11

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65

1

T68

13

T71

10

T85

7

auto[1]

55

1

T68

7

T71

10

T85

13

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62

1

T68

11

T71

9

T85

11

auto[1]

58

1

T68

9

T71

11

T85

9

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57

1

T68

13

T71

7

T85

11

auto[1]

63

1

T68

7

T71

13

T85

9

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64

1

T68

11

T71

10

T85

12

auto[1]

56

1

T68

9

T71

10

T85

8

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61

1

T68

8

T71

12

T85

9

auto[1]

59

1

T68

12

T71

8

T85

11

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61

1

T68

11

T71

10

T85

12

auto[1]

59

1

T68

9

T71

10

T85

8

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59

1

T68

13

T71

8

T85

11

auto[1]

61

1

T68

7

T71

12

T85

9

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68

1

T68

11

T71

10

T85

13

auto[1]

52

1

T68

9

T71

10

T85

7