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Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer

Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 239 1 T34 1 T269 102 T272 17
auto[1] 305 1 T13 1 T45 1 T44 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 256 1 T34 1 T269 126 T272 26
auto[1] 464 1 T13 1 T43 1 T44 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 232 1 T34 1 T269 112 T272 19
auto[1] 469 1 T8 1 T9 1 T13 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 217 1 T269 124 T272 25 T270 1
auto[1] 442 1 T9 1 T45 1 T41 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 241 1 T34 1 T269 110 T272 19
auto[1] 397 1 T43 1 T41 1 T42 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 236 1 T34 1 T269 122 T272 24
auto[1] 409 1 T8 1 T9 1 T44 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 202 1 T34 1 T269 108 T270 1
auto[1] 341 1 T9 1 T45 1 T44 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 278 1 T34 1 T269 128 T272 28
auto[1] 454 1 T8 1 T13 1 T45 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 228 1 T34 1 T269 114 T272 20
auto[1] 355 1 T45 1 T43 1 T41 3


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 273 1 T34 1 T35 1 T269 64
auto[1] 583 1 T269 64 T276 1 T270 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 208 1 T34 1 T269 48 T272 18
auto[1] 2318 1 T17 20 T27 20 T28 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 185 1 T35 1 T269 46 T272 17
auto[1] 2264 1 T17 18 T27 20 T28 16


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 243 1 T269 64 T272 24 T266 3
auto[1] 2235 1 T17 20 T27 19 T28 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 234 1 T269 62 T272 23 T323 1
auto[1] 2218 1 T17 20 T27 19 T28 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 213 1 T34 1 T269 60 T272 21
auto[1] 2254 1 T17 20 T27 20 T28 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 208 1 T269 58 T266 2 T277 1
auto[1] 2223 1 T17 19 T27 20 T28 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 241 1 T34 1 T35 1 T269 56
auto[1] 2314 1 T17 20 T27 19 T28 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 240 1 T34 1 T269 54 T272 19
auto[1] 2270 1 T17 20 T27 20 T28 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 153 1 T34 1 T269 44 T272 16
auto[1] 2276 1 T17 20 T27 20 T28 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 217 1 T34 1 T35 1 T269 52
auto[1] 2254 1 T17 20 T27 17 T28 16


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 168 1 T269 50 T272 18 T266 2
auto[1] 2225 1 T17 18 T27 20 T28 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 190 1 T34 1 T35 1 T269 42
auto[1] 2162 1 T17 20 T27 19 T28 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 207 1 T269 64 T272 35 T270 1
auto[1] 2207 1 T30 19 T31 19 T78 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 128 1 T34 1 T269 48 T270 1
auto[1] 2197 1 T30 20 T31 20 T78 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 161 1 T34 1 T269 62 T323 1
auto[1] 2238 1 T30 19 T31 19 T78 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 163 1 T269 46 T272 28 T323 1
auto[1] 2204 1 T30 18 T31 17 T78 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 168 1 T269 50 T272 30 T266 4
auto[1] 2209 1 T30 16 T31 19 T78 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 112 1 T269 34 T272 22 T266 3
auto[1] 2297 1 T30 19 T31 20 T78 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 172 1 T34 1 T269 58 T272 33
auto[1] 2258 1 T30 19 T31 20 T78 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 160 1 T269 42 T272 27 T323 1
auto[1] 2244 1 T30 20 T31 20 T78 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165 1 T269 56 T272 33 T270 1
auto[1] 2208 1 T30 19 T31 19 T78 15


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 130 1 T269 40 T272 26 T270 1
auto[1] 2243 1 T30 20 T31 20 T78 17


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 136 1 T34 1 T269 54 T272 32
auto[1] 2252 1 T30 20 T31 20 T78 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 116 1 T34 1 T269 38 T272 25
auto[1] 2133 1 T30 19 T31 20 T78 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 173 1 T269 60 T272 34 T270 1
auto[1] 2213 1 T30 19 T31 19 T78 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139 1 T34 1 T269 44 T272 28
auto[1] 2197 1 T30 20 T31 18 T78 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 185 1 T269 52 T272 31 T323 1
auto[1] 2201 1 T30 17 T31 20 T78 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 122 1 T34 1 T269 36 T272 24
auto[1] 2231 1 T30 20 T31 19 T78 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 265 1 T269 128 T270 1 T323 1
auto[1] 656 1 T4 1 T3 1 T10 3


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 317 1 T269 128 T272 31 T270 1
auto[1] 649 1 T4 1 T3 1 T10 3


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286 1 T34 1 T269 128 T271 1
auto[1] 705 1 T4 1 T3 1 T10 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%