Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1287

1

T1

11

T5

9

T2

9

auto[1]

1823

1

T1

16

T5

11

T2

18

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494

1

T1

14

T5

20

T2

18

auto[1]

616

1

T1

13

T2

9

T7

4

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2945

1

T1

27

T5

20

T2

27

auto[1]

165

1

T32

3

T33

1

T34

1

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2936

1

T1

27

T5

20

T2

23

auto[1]

174

1

T2

4

T7

4

T12

3

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2962

1

T1

27

T5

20

T2

24

auto[1]

148

1

T2

3

T31

1

T35

9

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1698

1

T1

1

T5

20

T2

6

auto[1]

1412

1

T1

26

T2

21

T52

19

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1270

1

T1

12

T5

13

T2

13

auto[1]

1840

1

T1

15

T5

7

T2

14

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1361

1

T1

11

T5

12

T2

12

auto[1]

1749

1

T1

16

T5

8

T2

15

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1266

1

T1

9

T5

7

T2

10

auto[1]

1844

1

T1

18

T5

13

T2

17

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1318

1

T1

7

T5

15

T2

10

auto[1]

1792

1

T1

20

T5

5

T2

17

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T48

1

T7

2

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T129

1

T37

2

T45

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T5

1

T48

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T157

1

T106

2

T251

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

35

1

T103

2

T88

2

T104

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T2

2

T129

2

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29

1

T5

1

T7

1

T52

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T1

3

T2

1

T129

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T5

3

T32

2

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T2

1

T129

1

T37

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T5

2

T35

1

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T1

1

T52

1

T37

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T1

1

T5

2

T27

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T130

1

T34

1

T105

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T2

1

T7

2

T31

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T135

1

T37

1

T314

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T5

1

T48

1

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T1

2

T52

1

T129

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32

1

T5

1

T48

1

T12

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T2

1

T35

1

T130

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T31

1

T271

1

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T35

1

T129

3

T130

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T12

1

T31

1

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T52

1

T31

9

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T5

1

T27

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T1

1

T2

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T5

1

T49

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T2

1

T52

1

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T216

1

T151

9

T139

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T52

2

T130

1

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

49

1

T131

7

T288

4

T282

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T35

1

T37

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T7

1

T32

2

T88

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T2

1

T52

2

T106

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T5

2

T7

1

T33

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

28

1

T12

1

T47

1

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T31

1

T47

1

T103

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T1

1

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T7

1

T32

1

T288

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T52

1

T130

1

T135

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T31

1

T216

1

T88

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T52

1

T130

1

T135

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T5

1

T27

1

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T1

3

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T47

9

T88

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

30

1

T130

2

T135

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T27

1

T48

1

T32

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T35

1

T153

3

T106

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T48

9

T12

1

T103

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T2

1

T52

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T32

2

T103

1

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T35

1

T34

1

T157

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T5

1

T12

9

T103

14

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T2

1

T52

1

T130

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T5

1

T27

9

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T1

1

T129

2

T130

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

75

1

T5

2

T7

1

T49

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

48

1

T52

1

T129

1

T33

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T7

1

T130

1

T271

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

81

1

T52

1

T135

1

T271

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

238

1

T2

5

T7

4

T35

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T1

1

T135

1

T37

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T35

1

T135

1

T314

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T45

2

T157

2

T153

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T130

1

T34

1

T314

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T130

1

T45

1

T34

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T2

1

T35

1

T344

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T2

1

T129

1

T34

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T1

1

T135

1

T45

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T2

1

T45

1

T157

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T35

2

T130

1

T276

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T1

1

T2

1

T35

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T45

1

T39

1

T344

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T1

1

T31

1

T35

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T39

1

T345

1

T346

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T130

1

T37

1

T157

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T1

1

T2

1

T130

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T31

1

T45

1

T39

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

10

1

T35

1

T130

1

T157

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T129

1

T39

1

T276

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T45

1

T314

1

T39

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T34

1

T314

1

T153

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T35

1

T157

1

T153

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T35

2

T135

1

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T1

1

T106

1

T344

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T2

1

T45

2

T34

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T2

1

T347

1

T279

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T1

1

T35

1

T276

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T34

1

T314

1

T153

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T37

1

T45

1

T153

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T344

1

T286

1

T348

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T33

2

T314

1

T349

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T129

1

T34

1

T314

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

198

1

T1

7

T2

2

T35

7

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T48

1

T7

2

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T35

1

T129

1

T135

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T5

1

T48

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

38

1

T45

2

T157

3

T153

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T103

2

T88

2

T104

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T2

2

T129

2

T130

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T5

1

T7

1

T52

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T1

3

T2

1

T129

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T5

3

T32

2

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T2

2

T35

1

T129

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T5

2

T35

1

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T1

1

T2

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T1

1

T5

2

T27

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T1

1

T130

1

T135

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T2

1

T7

2

T31

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

48

1

T2

1

T135

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T5

1

T48

1

T7

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T1

2

T52

1

T35

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T5

1

T48

1

T12

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T1

1

T2

2

T35

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T31

1

T271

1

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T35

1

T129

3

T130

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T12

1

T31

1

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T1

1

T52

1

T31

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

29

1

T5

1

T27

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T5

1

T49

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

30

1

T2

1

T52

1

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T216

1

T151

9

T139

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T1

1

T2

1

T52

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T131

7

T288

1

T282

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T31

1

T35

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T7

1

T32

2

T88

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

40

1

T2

1

T52

2

T35

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T5

2

T7

1

T33

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

43

1

T52

1

T35

1

T129

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T12

1

T47

1

T277

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T31

1

T47

1

T103

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T7

1

T32

2

T288

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

48

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T31

1

T216

1

T88

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T52

1

T35

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T5

1

T27

1

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

43

1

T1

4

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

74

1

T47

9

T88

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38

1

T2

1

T130

2

T135

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T27

1

T48

1

T32

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T2

1

T35

1

T153

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T48

9

T7

2

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T7

1

T32

2

T103

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T35

1

T34

2

T157

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T5

1

T12

9

T103

14

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T2

1

T52

1

T130

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T5

1

T27

9

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

1

T129

2

T130

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

72

1

T5

2

T7

1

T49

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T52

1

T129

1

T33

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T7

1

T130

1

T271

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

93

1

T52

1

T129

1

T135

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

161

1

T2

5

T7

4

T35

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

192

1

T1

8

T2

2

T35

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T349

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T237

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T237

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

22

1

T34

1

T314

2

T344

3

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T48

1

T7

2

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T35

1

T129

1

T135

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T5

1

T48

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

39

1

T45

2

T157

3

T153

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T103

2

T88

2

T104

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T2

2

T129

2

T130

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T5

1

T7

1

T52

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T1

3

T2

1

T129

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T5

3

T32

2

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T2

2

T35

1

T129

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T5

2

T35

1

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T1

1

T2

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T1

1

T5

2

T27

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T1

1

T130

1

T135

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

61

1

T2

1

T7

2

T31

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

48

1

T2

1

T135

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T5

1

T48

1

T7

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T1

2

T52

1

T35

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T5

1

T48

1

T12

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T1

1

T2

2

T35

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T31

1

T271

1

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T35

1

T129

3

T130

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T12

1

T31

1

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T1

1

T52

1

T31

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

29

1

T5

1

T27

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T5

1

T49

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

30

1

T2

1

T52

1

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T216

1

T151

7

T139

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T1

1

T2

1

T52

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T131

7

T288

4

T282

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T31

1

T35

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T7

1

T32

2

T88

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

41

1

T2

1

T52

2

T35

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T5

2

T7

1

T33

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

43

1

T52

1

T35

1

T129

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T12

1

T47

1

T277

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T31

1

T47

1

T103

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T7

1

T32

2

T288

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

48

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T31

1

T216

1

T88

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46

1

T52

1

T35

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T5

1

T27

1

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

43

1

T1

4

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T47

9

T88

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38

1

T2

1

T130

2

T135

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T27

1

T48

1

T32

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T2

1

T35

1

T153

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T48

9

T7

2

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T7

1

T32

2

T103

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T35

1

T34

2

T157

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

73

1

T5

1

T12

9

T103

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T2

1

T52

1

T130

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T5

1

T27

9

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

1

T129

2

T130

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

75

1

T5

2

T7

1

T49

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T52

1

T129

1

T33

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T7

1

T130

1

T271

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

93

1

T52

1

T129

1

T135

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

158

1

T2

2

T35

5

T130

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

168

1

T1

8

T2

1

T35

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T350

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T2

1

T129

1

T130

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T48

1

T7

2

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T35

1

T129

1

T135

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T5

1

T48

1

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

39

1

T45

2

T157

3

T153

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T103

2

T88

2

T104

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T2

2

T129

2

T130

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T5

1

T7

1

T52

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T1

3

T2

1

T129

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T5

3

T32

2

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T2

2

T35

1

T129

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T5

2

T35

1

T131

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T1

1

T2

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T1

1

T5

2

T27

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T1

1

T130

1

T135

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T2

1

T7

2

T31

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

48

1

T2

1

T135

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T5

1

T48

1

T7

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T1

2

T52

1

T35

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T5

1

T48

1

T12

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T1

1

T2

2

T35

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T31

1

T271

1

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T35

1

T129

3

T130

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T12

1

T31

1

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T1

1

T52

1

T31

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

29

1

T5

1

T27

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T5

1

T49

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

30

1

T2

1

T52

1

T129

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T216

1

T151

9

T139

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T1

1

T2

1

T52

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

49

1

T131

7

T288

4

T282

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T31

1

T35

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T7

1

T32

2

T88

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

41

1

T2

1

T52

2

T35

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T5

2

T7

1

T33

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

43

1

T52

1

T35

1

T129

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T12

1

T47

1

T277

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T31

1

T47

1

T103

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T7

1

T32

2

T288

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

48

1

T52

1

T35

1

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T31

1

T216

1

T88

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T52

1

T35

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T5

1

T27

1

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

43

1

T1

4

T2

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T47

9

T88

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38

1

T2

1

T130

2

T135

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

40

1

T27

1

T48

1

T32

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T2

1

T35

1

T153

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T48

9

T7

2

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T1

1

T2

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T7

1

T32

2

T103

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T35

1

T34

2

T157

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T5

1

T12

9

T103

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T2

1

T52

1

T130

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T5

1

T27

9

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

1

T129

2

T130

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

72

1

T5

2

T7

1

T49

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T52

1

T129

1

T33

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T7

1

T130

1

T271

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

93

1

T52

1

T129

1

T135

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

165

1

T2

3

T7

4

T129

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

186

1

T1

8

T2

1

T35

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T351

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T33

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T2

1

T35

4

T130

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded