Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T22 |
11 |
|
T23 |
8 |
|
T24 |
11 |
| auto[1] |
878 |
1 |
|
|
T22 |
9 |
|
T23 |
12 |
|
T24 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T22 |
8 |
|
T23 |
8 |
|
T24 |
12 |
| auto[1] |
872 |
1 |
|
|
T22 |
12 |
|
T23 |
12 |
|
T24 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T22 |
11 |
|
T23 |
5 |
|
T24 |
13 |
| auto[1] |
878 |
1 |
|
|
T22 |
9 |
|
T23 |
15 |
|
T24 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
863 |
1 |
|
|
T22 |
11 |
|
T23 |
8 |
|
T24 |
8 |
| auto[1] |
891 |
1 |
|
|
T22 |
9 |
|
T23 |
12 |
|
T24 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T22 |
8 |
|
T23 |
8 |
|
T24 |
11 |
| auto[1] |
925 |
1 |
|
|
T22 |
12 |
|
T23 |
12 |
|
T24 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T22 |
8 |
|
T23 |
13 |
|
T24 |
10 |
| auto[1] |
877 |
1 |
|
|
T22 |
12 |
|
T23 |
7 |
|
T24 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T22 |
11 |
|
T23 |
8 |
|
T24 |
8 |
| auto[1] |
907 |
1 |
|
|
T22 |
9 |
|
T23 |
12 |
|
T24 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
870 |
1 |
|
|
T22 |
14 |
|
T23 |
8 |
|
T24 |
12 |
| auto[1] |
884 |
1 |
|
|
T22 |
6 |
|
T23 |
12 |
|
T24 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T22 |
6 |
|
T23 |
10 |
|
T24 |
10 |
| auto[1] |
890 |
1 |
|
|
T22 |
14 |
|
T23 |
10 |
|
T24 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T22 |
13 |
|
T23 |
10 |
|
T24 |
7 |
| auto[1] |
870 |
1 |
|
|
T22 |
7 |
|
T23 |
10 |
|
T24 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T22 |
11 |
|
T23 |
13 |
|
T24 |
12 |
| auto[1] |
848 |
1 |
|
|
T22 |
9 |
|
T23 |
7 |
|
T24 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
874 |
1 |
|
|
T22 |
8 |
|
T23 |
11 |
|
T24 |
11 |
| auto[1] |
880 |
1 |
|
|
T22 |
12 |
|
T23 |
9 |
|
T24 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
911 |
1 |
|
|
T22 |
5 |
|
T23 |
11 |
|
T24 |
15 |
| auto[1] |
843 |
1 |
|
|
T22 |
15 |
|
T23 |
9 |
|
T24 |
5 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
881 |
1 |
|
|
T22 |
8 |
|
T23 |
8 |
|
T24 |
12 |
| auto[1] |
873 |
1 |
|
|
T22 |
12 |
|
T23 |
12 |
|
T24 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T22 |
9 |
|
T23 |
10 |
|
T24 |
8 |
| auto[1] |
862 |
1 |
|
|
T22 |
11 |
|
T23 |
10 |
|
T24 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
857 |
1 |
|
|
T22 |
9 |
|
T23 |
7 |
|
T24 |
7 |
| auto[1] |
897 |
1 |
|
|
T22 |
11 |
|
T23 |
13 |
|
T24 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T22 |
11 |
|
T23 |
3 |
|
T24 |
10 |
| auto[1] |
896 |
1 |
|
|
T22 |
9 |
|
T23 |
17 |
|
T24 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
846 |
1 |
|
|
T22 |
11 |
|
T23 |
10 |
|
T24 |
5 |
| auto[1] |
908 |
1 |
|
|
T22 |
9 |
|
T23 |
10 |
|
T24 |
15 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T22 |
8 |
|
T23 |
8 |
|
T24 |
11 |
| auto[1] |
887 |
1 |
|
|
T22 |
12 |
|
T23 |
12 |
|
T24 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T22 |
13 |
|
T23 |
14 |
|
T24 |
9 |
| auto[1] |
886 |
1 |
|
|
T22 |
7 |
|
T23 |
6 |
|
T24 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T22 |
10 |
|
T23 |
9 |
|
T24 |
7 |
| auto[1] |
940 |
1 |
|
|
T22 |
10 |
|
T23 |
11 |
|
T24 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T22 |
7 |
|
T23 |
11 |
|
T24 |
10 |
| auto[1] |
890 |
1 |
|
|
T22 |
13 |
|
T23 |
9 |
|
T24 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T22 |
9 |
|
T23 |
10 |
|
T24 |
9 |
| auto[1] |
876 |
1 |
|
|
T22 |
11 |
|
T23 |
10 |
|
T24 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
874 |
1 |
|
|
T22 |
8 |
|
T23 |
11 |
|
T24 |
11 |
| auto[1] |
880 |
1 |
|
|
T22 |
12 |
|
T23 |
9 |
|
T24 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
446 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T24 |
4 |
| auto[0] |
auto[1] |
446 |
1 |
|
|
T22 |
5 |
|
T23 |
9 |
|
T24 |
4 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T22 |
7 |
|
T23 |
4 |
|
T24 |
9 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T22 |
4 |
|
T23 |
6 |
|
T24 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T24 |
1 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T22 |
5 |
|
T23 |
6 |
|
T24 |
6 |
| auto[1] |
auto[0] |
441 |
1 |
|
|
T22 |
7 |
|
T23 |
7 |
|
T24 |
7 |
| auto[1] |
auto[1] |
456 |
1 |
|
|
T22 |
4 |
|
T23 |
6 |
|
T24 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T22 |
4 |
|
T23 |
3 |
|
T24 |
7 |
| auto[0] |
auto[1] |
442 |
1 |
|
|
T22 |
7 |
|
T24 |
3 |
|
T11 |
5 |
| auto[1] |
auto[0] |
413 |
1 |
|
|
T22 |
4 |
|
T23 |
5 |
|
T24 |
4 |
| auto[1] |
auto[1] |
483 |
1 |
|
|
T22 |
5 |
|
T23 |
12 |
|
T24 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T22 |
4 |
|
T23 |
9 |
|
T24 |
4 |
| auto[0] |
auto[1] |
412 |
1 |
|
|
T22 |
7 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T22 |
4 |
|
T23 |
4 |
|
T24 |
6 |
| auto[1] |
auto[1] |
465 |
1 |
|
|
T22 |
5 |
|
T23 |
6 |
|
T24 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
409 |
1 |
|
|
T22 |
5 |
|
T23 |
1 |
|
T24 |
3 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T22 |
3 |
|
T23 |
7 |
|
T24 |
8 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T22 |
6 |
|
T23 |
7 |
|
T24 |
5 |
| auto[1] |
auto[1] |
449 |
1 |
|
|
T22 |
6 |
|
T23 |
5 |
|
T24 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
421 |
1 |
|
|
T22 |
9 |
|
T23 |
4 |
|
T24 |
4 |
| auto[0] |
auto[1] |
447 |
1 |
|
|
T22 |
4 |
|
T23 |
10 |
|
T24 |
5 |
| auto[1] |
auto[0] |
449 |
1 |
|
|
T22 |
5 |
|
T23 |
4 |
|
T24 |
8 |
| auto[1] |
auto[1] |
437 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T24 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T22 |
4 |
|
T23 |
7 |
|
T24 |
1 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T22 |
3 |
|
T23 |
4 |
|
T24 |
9 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T22 |
9 |
|
T23 |
3 |
|
T24 |
6 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T22 |
4 |
|
T23 |
6 |
|
T24 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
459 |
1 |
|
|
T22 |
4 |
|
T23 |
8 |
|
T24 |
3 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T24 |
6 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T22 |
7 |
|
T23 |
5 |
|
T24 |
9 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T22 |
4 |
|
T23 |
5 |
|
T24 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
471 |
1 |
|
|
T22 |
3 |
|
T23 |
4 |
|
T24 |
9 |
| auto[0] |
auto[1] |
440 |
1 |
|
|
T22 |
2 |
|
T23 |
7 |
|
T24 |
6 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T22 |
8 |
|
T23 |
4 |
|
T24 |
2 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T22 |
7 |
|
T23 |
5 |
|
T24 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
881 |
1 |
|
|
T22 |
8 |
|
T23 |
8 |
|
T24 |
12 |
| auto[1] |
auto[1] |
872 |
1 |
|
|
T22 |
12 |
|
T23 |
12 |
|
T24 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T22 |
3 |
|
T23 |
3 |
|
T24 |
5 |
| auto[0] |
auto[1] |
406 |
1 |
|
|
T22 |
7 |
|
T23 |
6 |
|
T24 |
2 |
| auto[1] |
auto[0] |
456 |
1 |
|
|
T22 |
3 |
|
T23 |
7 |
|
T24 |
5 |
| auto[1] |
auto[1] |
484 |
1 |
|
|
T22 |
7 |
|
T23 |
4 |
|
T24 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
874 |
1 |
|
|
T22 |
8 |
|
T23 |
11 |
|
T24 |
11 |
| auto[1] |
auto[1] |
880 |
1 |
|
|
T22 |
12 |
|
T23 |
9 |
|
T24 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T38 |
9 |
|
T105 |
11 |
|
T39 |
12 |
| auto[1] |
173 |
1 |
|
|
T38 |
11 |
|
T105 |
9 |
|
T39 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T38 |
13 |
|
T105 |
10 |
|
T39 |
11 |
| auto[1] |
137 |
1 |
|
|
T38 |
7 |
|
T105 |
10 |
|
T39 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T38 |
11 |
|
T105 |
13 |
|
T39 |
10 |
| auto[1] |
167 |
1 |
|
|
T38 |
9 |
|
T105 |
7 |
|
T39 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T38 |
8 |
|
T105 |
11 |
|
T39 |
9 |
| auto[1] |
185 |
1 |
|
|
T38 |
12 |
|
T105 |
9 |
|
T39 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T38 |
11 |
|
T105 |
11 |
|
T39 |
14 |
| auto[1] |
147 |
1 |
|
|
T38 |
9 |
|
T105 |
9 |
|
T39 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T38 |
11 |
|
T105 |
15 |
|
T39 |
9 |
| auto[1] |
139 |
1 |
|
|
T38 |
9 |
|
T105 |
5 |
|
T39 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T38 |
14 |
|
T105 |
7 |
|
T39 |
8 |
| auto[1] |
164 |
1 |
|
|
T38 |
6 |
|
T105 |
13 |
|
T39 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
172 |
1 |
|
|
T38 |
9 |
|
T105 |
16 |
|
T39 |
8 |
| auto[1] |
148 |
1 |
|
|
T38 |
11 |
|
T105 |
4 |
|
T39 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T38 |
8 |
|
T105 |
9 |
|
T39 |
9 |
| auto[1] |
161 |
1 |
|
|
T38 |
12 |
|
T105 |
11 |
|
T39 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T38 |
11 |
|
T105 |
9 |
|
T39 |
10 |
| auto[1] |
169 |
1 |
|
|
T38 |
9 |
|
T105 |
11 |
|
T39 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T38 |
13 |
|
T105 |
7 |
|
T39 |
8 |
| auto[1] |
165 |
1 |
|
|
T38 |
7 |
|
T105 |
13 |
|
T39 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T38 |
9 |
|
T105 |
10 |
|
T39 |
9 |
| auto[1] |
161 |
1 |
|
|
T38 |
11 |
|
T105 |
10 |
|
T39 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T38 |
11 |
|
T105 |
7 |
|
T39 |
10 |
| auto[1] |
159 |
1 |
|
|
T38 |
9 |
|
T105 |
13 |
|
T39 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T38 |
13 |
|
T105 |
10 |
|
T39 |
11 |
| auto[1] |
137 |
1 |
|
|
T38 |
7 |
|
T105 |
10 |
|
T39 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T38 |
15 |
|
T105 |
11 |
|
T39 |
14 |
| auto[1] |
143 |
1 |
|
|
T38 |
5 |
|
T105 |
9 |
|
T39 |
6 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T38 |
12 |
|
T105 |
9 |
|
T39 |
13 |
| auto[1] |
165 |
1 |
|
|
T38 |
8 |
|
T105 |
11 |
|
T39 |
7 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T38 |
14 |
|
T105 |
11 |
|
T39 |
11 |
| auto[1] |
155 |
1 |
|
|
T38 |
6 |
|
T105 |
9 |
|
T39 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T38 |
8 |
|
T105 |
11 |
|
T39 |
6 |
| auto[1] |
159 |
1 |
|
|
T38 |
12 |
|
T105 |
9 |
|
T39 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T38 |
9 |
|
T105 |
10 |
|
T39 |
9 |
| auto[1] |
160 |
1 |
|
|
T38 |
11 |
|
T105 |
10 |
|
T39 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T38 |
10 |
|
T105 |
11 |
|
T39 |
7 |
| auto[1] |
162 |
1 |
|
|
T38 |
10 |
|
T105 |
9 |
|
T39 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T38 |
8 |
|
T105 |
7 |
|
T39 |
10 |
| auto[1] |
169 |
1 |
|
|
T38 |
12 |
|
T105 |
13 |
|
T39 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T38 |
6 |
|
T105 |
5 |
|
T39 |
10 |
| auto[1] |
172 |
1 |
|
|
T38 |
14 |
|
T105 |
15 |
|
T39 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
168 |
1 |
|
|
T38 |
10 |
|
T105 |
13 |
|
T39 |
10 |
| auto[1] |
152 |
1 |
|
|
T38 |
10 |
|
T105 |
7 |
|
T39 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T38 |
9 |
|
T105 |
10 |
|
T39 |
9 |
| auto[1] |
161 |
1 |
|
|
T38 |
11 |
|
T105 |
10 |
|
T39 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T38 |
7 |
|
T105 |
5 |
|
T39 |
8 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T38 |
8 |
|
T105 |
6 |
|
T39 |
6 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T38 |
4 |
|
T105 |
8 |
|
T39 |
2 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T38 |
1 |
|
T105 |
1 |
|
T39 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T38 |
4 |
|
T105 |
3 |
|
T39 |
7 |
| auto[0] |
auto[1] |
89 |
1 |
|
|
T38 |
8 |
|
T105 |
6 |
|
T39 |
6 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T38 |
4 |
|
T105 |
8 |
|
T39 |
2 |
| auto[1] |
auto[1] |
96 |
1 |
|
|
T38 |
4 |
|
T105 |
3 |
|
T39 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
99 |
1 |
|
|
T38 |
6 |
|
T105 |
6 |
|
T39 |
8 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T38 |
8 |
|
T105 |
5 |
|
T39 |
3 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T38 |
5 |
|
T105 |
5 |
|
T39 |
6 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T38 |
1 |
|
T105 |
4 |
|
T39 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
101 |
1 |
|
|
T38 |
3 |
|
T105 |
8 |
|
T39 |
3 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T38 |
5 |
|
T105 |
3 |
|
T39 |
3 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T38 |
8 |
|
T105 |
7 |
|
T39 |
6 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T38 |
4 |
|
T105 |
2 |
|
T39 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T38 |
5 |
|
T105 |
3 |
|
T39 |
3 |
| auto[0] |
auto[1] |
86 |
1 |
|
|
T38 |
4 |
|
T105 |
7 |
|
T39 |
6 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T38 |
9 |
|
T105 |
4 |
|
T39 |
5 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T38 |
2 |
|
T105 |
6 |
|
T39 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T38 |
3 |
|
T105 |
8 |
|
T39 |
2 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T38 |
7 |
|
T105 |
3 |
|
T39 |
5 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T38 |
6 |
|
T105 |
8 |
|
T39 |
6 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T38 |
4 |
|
T105 |
1 |
|
T39 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T38 |
4 |
|
T105 |
3 |
|
T39 |
5 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T38 |
2 |
|
T105 |
2 |
|
T39 |
5 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T38 |
7 |
|
T105 |
6 |
|
T39 |
5 |
| auto[1] |
auto[1] |
86 |
1 |
|
|
T38 |
7 |
|
T105 |
9 |
|
T39 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T38 |
7 |
|
T105 |
6 |
|
T39 |
4 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T38 |
3 |
|
T105 |
7 |
|
T39 |
6 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T38 |
6 |
|
T105 |
1 |
|
T39 |
4 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T38 |
4 |
|
T105 |
6 |
|
T39 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T38 |
3 |
|
T105 |
3 |
|
T39 |
5 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T38 |
8 |
|
T105 |
4 |
|
T39 |
5 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T38 |
6 |
|
T105 |
8 |
|
T39 |
7 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T38 |
3 |
|
T105 |
5 |
|
T39 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
183 |
1 |
|
|
T38 |
13 |
|
T105 |
10 |
|
T39 |
11 |
| auto[1] |
auto[1] |
137 |
1 |
|
|
T38 |
7 |
|
T105 |
10 |
|
T39 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T38 |
3 |
|
T105 |
1 |
|
T39 |
5 |
| auto[0] |
auto[1] |
76 |
1 |
|
|
T38 |
5 |
|
T105 |
6 |
|
T39 |
5 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T38 |
5 |
|
T105 |
8 |
|
T39 |
4 |
| auto[1] |
auto[1] |
85 |
1 |
|
|
T38 |
7 |
|
T105 |
5 |
|
T39 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
159 |
1 |
|
|
T38 |
9 |
|
T105 |
10 |
|
T39 |
9 |
| auto[1] |
auto[1] |
161 |
1 |
|
|
T38 |
11 |
|
T105 |
10 |
|
T39 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T38 |
6 |
|
T39 |
8 |
|
T122 |
10 |
| auto[1] |
48 |
1 |
|
|
T38 |
14 |
|
T39 |
12 |
|
T122 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
36 |
1 |
|
|
T38 |
7 |
|
T39 |
9 |
|
T122 |
8 |
| auto[1] |
44 |
1 |
|
|
T38 |
13 |
|
T39 |
11 |
|
T122 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T38 |
14 |
|
T39 |
11 |
|
T122 |
12 |
| auto[1] |
34 |
1 |
|
|
T38 |
6 |
|
T39 |
9 |
|
T122 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T38 |
14 |
|
T39 |
7 |
|
T122 |
11 |
| auto[1] |
38 |
1 |
|
|
T38 |
6 |
|
T39 |
13 |
|
T122 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T38 |
7 |
|
T39 |
10 |
|
T122 |
9 |
| auto[1] |
46 |
1 |
|
|
T38 |
13 |
|
T39 |
10 |
|
T122 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
38 |
1 |
|
|
T38 |
10 |
|
T39 |
8 |
|
T122 |
10 |
| auto[1] |
42 |
1 |
|
|
T38 |
10 |
|
T39 |
12 |
|
T122 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
38 |
1 |
|
|
T38 |
12 |
|
T39 |
11 |
|
T122 |
9 |
| auto[1] |
42 |
1 |
|
|
T38 |
8 |
|
T39 |
9 |
|
T122 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
37 |
1 |
|
|
T38 |
9 |
|
T39 |
8 |
|
T122 |
13 |
| auto[1] |
43 |
1 |
|
|
T38 |
11 |
|
T39 |
12 |
|
T122 |
7 |