Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T1

12

T6

4

T3

1

auto[1]

1699

1

T1

14

T6

10

T3

22

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2370

1

T1

21

T6

14

T3

23

auto[1]

483

1

T1

5

T7

6

T9

7

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2685

1

T1

26

T6

14

T3

17

auto[1]

168

1

T3

6

T32

6

T33

9

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2722

1

T1

20

T6

14

T3

23

auto[1]

131

1

T1

6

T26

5

T34

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2680

1

T1

26

T6

14

T3

23

auto[1]

173

1

T9

7

T10

4

T32

4

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1737

1

T1

26

T6

14

T3

23

auto[1]

1116

1

T7

22

T10

20

T46

9

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T1

12

T6

14

T3

3

auto[1]

1727

1

T1

14

T3

20

T7

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T1

12

T6

6

T3

7

auto[1]

1760

1

T1

14

T6

8

T3

16

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1264

1

T1

10

T6

5

T3

6

auto[1]

1589

1

T1

16

T6

9

T3

17

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1186

1

T1

10

T6

14

T3

23

auto[1]

1667

1

T1

16

T7

14

T9

20

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T1

1

T6

1

T50

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T32

2

T249

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T1

1

T6

2

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T249

1

T256

1

T90

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T1

1

T34

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T32

1

T249

1

T174

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T9

1

T26

1

T106

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T7

2

T10

1

T256

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T1

1

T6

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T7

1

T250

3

T256

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T1

1

T6

1

T3

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T10

1

T32

2

T252

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T206

1

T253

1

T324

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T32

1

T249

1

T256

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T9

1

T247

3

T253

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T114

1

T250

2

T256

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T6

1

T26

1

T85

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T46

1

T252

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T1

1

T6

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T7

1

T10

1

T249

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T1

1

T26

1

T34

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T10

1

T32

1

T85

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T26

1

T34

5

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T7

1

T86

7

T250

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T9

1

T26

1

T106

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T114

2

T256

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T6

6

T3

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T10

1

T32

1

T252

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

26

1

T1

1

T42

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T7

1

T10

2

T66

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T1

1

T67

9

T206

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

72

1

T248

4

T259

9

T250

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T1

1

T9

2

T66

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T10

2

T42

1

T249

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T3

5

T66

5

T42

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T7

1

T66

2

T249

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T26

1

T46

1

T247

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T78

1

T90

2

T325

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T26

1

T106

2

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T256

1

T91

1

T327

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T34

1

T42

1

T246

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T7

1

T10

1

T328

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T42

1

T246

6

T247

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T249

1

T248

4

T252

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

30

1

T1

2

T26

1

T34

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T250

1

T256

2

T91

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

64

1

T1

1

T9

1

T68

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T7

2

T32

1

T247

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

32

1

T34

2

T206

1

T248

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T329

1

T91

1

T183

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T3

1

T46

1

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T10

1

T32

2

T114

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T7

1

T9

2

T26

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T7

1

T114

1

T250

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T1

1

T26

3

T106

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

88

1

T10

1

T245

9

T249

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

32

1

T3

1

T46

1

T248

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T248

1

T90

1

T95

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T3

13

T9

1

T106

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T1

1

T9

1

T26

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

62

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

294

1

T1

6

T9

8

T10

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T10

1

T114

1

T33

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T32

1

T114

1

T256

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T91

1

T325

1

T174

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T42

1

T183

1

T330

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T249

1

T252

1

T250

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T10

1

T174

1

T331

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T249

1

T252

1

T183

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T249

1

T252

2

T92

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T33

2

T183

1

T174

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T330

1

T332

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T92

1

T95

1

T262

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T183

1

T92

1

T96

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T33

1

T331

1

T333

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T66

2

T325

2

T334

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T7

1

T32

1

T331

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T66

1

T252

1

T33

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T92

1

T327

1

T335

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T33

1

T174

2

T331

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T10

1

T66

4

T249

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T10

1

T249

1

T252

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T7

1

T32

1

T114

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T32

1

T249

1

T328

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T10

1

T114

1

T254

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T252

1

T250

1

T90

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T247

8

T92

2

T336

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T329

3

T327

1

T330

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T252

3

T337

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T252

2

T114

1

T331

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T7

1

T249

1

T78

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T248

1

T33

1

T183

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T32

1

T158

5

T33

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T32

1

T330

1

T95

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

89

1

T7

3

T10

1

T42

1

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	31	65	67.71	31
Automatically Generated Cross Bins	96	31	65	67.71	31
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T1

1

T6

1

T50

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T7

1

T32

3

T249

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T1

2

T6

2

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T249

1

T256

1

T90

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T1

1

T34

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T32

1

T42

1

T249

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T9

1

T26

1

T106

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T7

2

T10

1

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T1

1

T6

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T7

1

T10

1

T250

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T1

2

T6

1

T3

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T10

1

T32

2

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T206

2

T253

1

T324

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T32

1

T249

2

T252

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

33

1

T9

1

T247

3

T253

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T114

1

T250

2

T256

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T6

1

T26

1

T85

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T7

1

T46

1

T252

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T1

1

T6

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T7

1

T10

1

T249

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T1

1

T26

1

T34

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T10

1

T32

1

T85

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T9

1

T26

1

T34

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T86

7

T250

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T1

1

T9

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T7

1

T66

2

T114

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T6

6

T3

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T7

1

T10

1

T32

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T1

1

T42

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T7

1

T10

2

T66

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

54

1

T1

1

T67

9

T206

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

79

1

T248

4

T259

9

T250

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T1

2

T9

2

T66

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T10

2

T42

1

T249

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T3

3

T66

5

T42

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T7

1

T10

1

T66

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T26

1

T46

1

T247

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T10

1

T249

1

T252

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T26

1

T106

2

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T7

1

T32

1

T114

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T34

1

T42

1

T246

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T10

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T42

1

T246

6

T247

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T10

1

T249

1

T248

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

33

1

T1

2

T9

1

T26

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T252

1

T250

2

T256

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

66

1

T1

1

T9

1

T68

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T7

2

T32

1

T247

17

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T34

2

T206

1

T248

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T329

4

T91

1

T183

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T3

1

T46

1

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T10

1

T32

2

T252

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T1

1

T7

1

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T7

1

T252

2

T114

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

68

1

T1

1

T9

1

T26

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

100

1

T7

1

T10

1

T245

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T3

1

T9

1

T46

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T248

2

T33

1

T90

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T3

9

T9

1

T106

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

78

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T1

1

T9

2

T26

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

71

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

176

1

T1

6

T9

9

T10

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

90

1

T7

3

T10

2

T42

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T33

2

T330

6

T334

5

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T1

1

T6

1

T50

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T7

1

T32

3

T249

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T1

2

T6

2

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T249

1

T256

1

T90

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T1

1

T34

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T32

1

T42

1

T249

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T9

1

T26

1

T106

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T7

2

T10

1

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T1

1

T6

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T7

1

T10

1

T250

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T1

2

T6

1

T3

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T10

1

T32

2

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T206

2

T253

1

T324

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T32

1

T249

2

T252

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

33

1

T9

1

T247

3

T253

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T114

1

T250

2

T256

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T6

1

T26

1

T85

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T7

1

T46

1

T252

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T1

1

T6

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T7

1

T10

1

T249

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T1

1

T26

1

T34

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T10

1

T32

1

T85

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T9

1

T26

1

T34

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T86

7

T250

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T1

1

T9

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T7

1

T114

2

T256

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T6

6

T3

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T7

1

T10

1

T32

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

31

1

T1

1

T42

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T7

1

T10

2

T66

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T1

1

T67

9

T206

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

79

1

T248

4

T259

9

T250

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T1

2

T9

2

T66

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T10

2

T42

1

T249

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T3

5

T66

4

T42

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T7

1

T10

1

T66

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T26

1

T46

1

T247

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T10

1

T249

1

T252

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T26

1

T106

2

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T7

1

T32

1

T114

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T34

1

T42

1

T246

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T10

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T42

1

T246

6

T247

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T10

1

T249

1

T248

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

33

1

T1

2

T9

1

T26

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T252

1

T250

2

T256

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

67

1

T1

1

T9

1

T68

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T7

2

T32

1

T247

17

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T34

2

T206

1

T248

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T329

1

T91

1

T183

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T3

1

T46

1

T106

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T10

1

T32

2

T252

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T1

1

T7

1

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T7

1

T252

2

T114

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

73

1

T1

1

T9

1

T26

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

100

1

T7

1

T10

1

T245

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

33

1

T3

1

T9

1

T46

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T248

2

T33

1

T90

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

73

1

T3

13

T9

1

T106

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

78

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T1

1

T9

2

T26

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

71

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

221

1

T9

9

T10

4

T32

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

87

1

T7

3

T10

2

T42

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T338

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T66

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T329

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T252

1

T183

4

T174

4

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T1

1

T6

1

T50

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T7

1

T32

3

T249

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T1

2

T6

2

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T249

1

T256

1

T90

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T1

1

T34

1

T66

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T32

1

T42

1

T249

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T9

1

T26

1

T106

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T7

2

T10

1

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T1

1

T6

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T7

1

T10

1

T250

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T1

2

T6

1

T3

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T10

1

T32

2

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T206

2

T253

1

T324

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T32

1

T249

2

T252

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

33

1

T9

1

T247

3

T253

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T114

1

T250

2

T256

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T6

1

T26

1

T85

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T7

1

T46

1

T252

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T1

1

T6

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T7

1

T10

1

T249

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T1

1

T26

1

T34

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T10

1

T32

1

T85

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T9

1

T26

1

T34

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T86

7

T250

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T1

1

T9

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T7

1

T66

2

T114

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T6

6

T3

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T7

1

T10

1

T32

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T1

1

T42

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T7

1

T10

2

T66

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

54

1

T1

1

T67

9

T206

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

79

1

T248

4

T259

9

T250

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T1

2

T9

2

T66

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T10

2

T42

1

T249

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T3

5

T66

1

T42

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T7

1

T10

1

T66

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T26

1

T46

1

T247

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T10

1

T249

1

T252

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T26

1

T106

2

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T7

1

T32

1

T114

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T34

1

T42

1

T246

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T10

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T42

1

T246

6

T247

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T10

1

T249

1

T248

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

33

1

T1

2

T9

1

T26

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T252

1

T250

2

T256

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

67

1

T1

1

T9

1

T68

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T7

2

T32

1

T247

17

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T34

2

T206

1

T248

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T329

1

T91

1

T183

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T3

1

T46

1

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T10

1

T32

2

T252

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T1

1

T7

1

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T7

1

T252

2

T114

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

76

1

T1

1

T9

1

T26

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

100

1

T7

1

T10

1

T245

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T3

1

T9

1

T46

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T248

2

T33

1

T90

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

72

1

T3

13

T9

1

T106

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

78

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T1

1

T9

2

T26

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

71

1

T7

1

T10

1

T46

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

170

1

T1

6

T9

2

T32

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

93

1

T7

3

T10

2

T42

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T329

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T249

2

T33

1

T325

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded